Patents by Inventor Tomotsugu GOTO

Tomotsugu GOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and data writing method using a checkerboard pattern utilizing existing data supply bit addresses
    Patent number: 9564196
    Abstract: To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity by making a change of a simple circuit configuration free from the need of a data holding circuit and a voltage converting circuit large in circuit area in a memory array in which the order of arrangement of bits is reversedly arranged between data words adjacent in a row direction. A row decoder and a column decoder are respectively configured to enable operation switching to an all selection mode and an even/odd-based selection mode in addition to a single address selection mode of a memory array by a control signal from a control circuit.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: February 7, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Tomotsugu Goto
  • SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD
    Publication number: 20160225416
    Abstract: To provide a semiconductor memory device capable of writing a checkerboard pattern for interference and investigation by three writings regardless of the magnitude of memory capacity by making a change of a simple circuit configuration free from the need of a data holding circuit and a voltage converting circuit large in circuit area in a memory array in which the order of arrangement of bits is reversedly arranged between data words adjacent in a row direction. A row decoder and a column decoder are respectively configured to enable operation switching to an all selection mode and an even/odd-based selection mode in addition to a single address selection mode of a memory array by a control signal from a control circuit.
    Type: Application
    Filed: January 21, 2016
    Publication date: August 4, 2016
    Inventor: Tomotsugu GOTO