Patents by Inventor Tomoya Baba

Tomoya Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10259032
    Abstract: Metal foil base material placed on lower blade is first restricted under pressure by lower blade and pad and then cut by a shearing action based on an engagement of lower blade side cutting edge and upper blade side cutting edge. Resin face sheets are fixed to the top surface of lower blade and the pressing surface of pad, the face sheets having a larger friction coefficient than that of these surfaces. By frictional forces imparted by face sheets, metal foil base material is prevented from being dragged and moved by the pressing force of the upper blade prior to cutting. Consequently, the occurrence of “burr”, “roll-up”, and so forth is eliminated thereby ensuring a good cutting quality.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: April 16, 2019
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Jun Ikeuchi, Kazuhiro Mitamura, Masaki Saito, Motoo Shimizu, Takeshi Iwata, Kuniyoshi Wakamatsu, Toshiaki Ohrui, Tomoya Baba
  • Publication number: 20160214266
    Abstract: Metal foil base material placed on lower blade is first restricted under pressure by lower blade and pad and then cut by a shearing action based on an engagement of lower blade side cutting edge and upper blade side cutting edge. Resin face sheets are fixed to the top surface of lower blade and the pressing surface of pad, the face sheets having a larger friction coefficient than that of these surfaces. By frictional forces imparted by face sheets, metal foil base material is prevented from being dragged and moved by the pressing force of the upper blade prior to cutting. Consequently, the occurrence of “burr”, “roll-up”, and so forth is eliminated thereby ensuring a good cutting quality.
    Type: Application
    Filed: July 17, 2014
    Publication date: July 28, 2016
    Inventors: Jun Ikeuchi, Kazuhiro Mitamura, Masaki Saito, Motoo Shimizu, Takeshi Iwata, Kuniyoshi Wakamatsu, Toshiaki Ohrui, Tomoya Baba
  • Patent number: 7348186
    Abstract: A method of improving a semiconductor substrate including a SiGe film on a Si or SOI substrate is provided. The method includes determining a relationship between a film condition of the SiGe film and a hydrogen ion implantation condition used in making the SiGe film so as to achieve relaxation of lattice distortion in the SiGe film as well as improved crystallinity and/or surface condition of the SiGe film, so that improved conditions for improving quality of the SiGe film on the Si or SOI substrate can be determined.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: March 25, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akira Yoshida, Tomoya Baba
  • Patent number: 6852604
    Abstract: A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiGe layer in the substrate that become element isolation formation regions, and carrying out a heat treatment.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: February 8, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoya Baba
  • Patent number: 6774409
    Abstract: A semiconductor device comprises: a semiconductor substrate on which a silicon germanium film, a carbon-containing silicon film and a silicon film are formed in this order and a gate electrode on the semiconductor substrate with intervention of a gate oxide film, wherein a channel region of the semiconductor device the is formed in the carbon-containing silicon film or wherein a channel region of the semiconductor device is formed in the silicon germanium film.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomoya Baba, Katsumasa Fujii, Akiyoshi Mutou
  • Patent number: 6750100
    Abstract: A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: June 15, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Sheng Teng Hsu, Tomoya Baba, Tetsuya Ohnishi
  • Publication number: 20040058482
    Abstract: A method for improving a semiconductor substrate having a SiGe film on a Si or SOI substrate by using a hydrogen ion implantation and an annealing, wherein the hydrogen ion implantation comprises the steps of:
    Type: Application
    Filed: August 13, 2003
    Publication date: March 25, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akira Yoshida, Tomoya Baba
  • Publication number: 20030219954
    Abstract: A manufacturing method of a semiconductor substrate comprising the steps of: (a) forming a SiGe layer on a substrate of which the surface is made of silicon; (b) further forming a semiconductor layer on the SiGe layer; and (c) implanting ions into regions of the SiGe layer in the substrate that become element isolation formation regions, and carrying out a heat treatment.
    Type: Application
    Filed: April 30, 2003
    Publication date: November 27, 2003
    Inventor: Tomoya Baba
  • Publication number: 20030040156
    Abstract: A method of forming a memory device includes preparing a substrate having predefined characteristics; forming a first layer set on the substrate, including: building a first forming layer, having first form segments, on the substrate; building placeholder sidewalls on the first form segments wherein the sidewalls have a thickness of between about one nm and 100 nm; building a second forming layer, having second form segments, on the substrate between the placeholder sidewalls; removing the placeholder sidewalls forming vacated areas; and building active devices in the vacated areas.
    Type: Application
    Filed: August 27, 2001
    Publication date: February 27, 2003
    Inventors: Sheng Teng Hsu, Tomoya Baba, Tetsuya Ohnishi
  • Publication number: 20020125502
    Abstract: A semiconductor device comprises: a semiconductor substrate on which a silicon germanium film, a carbon-containing silicon film and a silicon film are formed in this order and a gate electrode on the semiconductor substrate with intervention of a gate oxide film, wherein a channel region of the semiconductor device the is formed in the carbon-containing silicon film or wherein a channel region of the semiconductor device is formed in the silicon germanium film.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 12, 2002
    Inventors: Tomoya Baba, Katsumasa Fujii, Akiyoshi Mutou
  • Patent number: 5532508
    Abstract: A method for manufacturing a semiconductor device including steps of forming a gate oxide film and a gate electrode on a semiconductor substrate; implanting impurity ions of the same conductivity as the substrate in an oblique direction at a first tilt angle to the normal line of the substrate and with a first acceleration voltage and dose, while rotating the substrate about the normal line thereof; implanting impurities of the same conductivity as the substrate in the same manner except for using a tilt angle to the normal line which is greater and a dose which is smaller than that of the first tilt angle and dose; and forming source and drain regions by implanting impurity ions of the opposite conductivity to the substrate into the substrate, followed by performing a thermal treatment.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: July 2, 1996
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiji Kaneko, Tomoya Baba
  • Patent number: 5426063
    Abstract: A method for manufacturing a semiconductor device including steps of forming a gate oxide film and a gate electrode on a semiconductor substrate; implanting impurity ions of the same conductivity as the substrate in an oblique direction at a first tilt angle to the normal line of the substrate and with a first acceleration voltage and dose, while rotating the substrate about the normal line thereof; implanting impurities of the same conductivity as the substrate in the same manner except for using a tilt angle to the normal line which is greater and a dose is smaller than that of the first tilt angle and dose; and forming source and drain regions by implanting impurity ions of the opposite conductivity to the substrate into the substrate, followed by performing a thermal treatment.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: June 20, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiji Kaneko, Tomoya Baba