Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Abstract: According to one embodiment, a memory card includes a nonvolatile memory including a data storage region and storing a table in which a logical address received from a host device is mapped to a physical address in the data storage region, and a controller configured to control the nonvolatile memory. The controller exchanges a first logical address with a second logical address based on a first command and data received from the host device.

Abstract: According to one embodiment, a memory card includes a nonvolatile memory including a data storage region and storing a table in which a logical address received from a host device is mapped to a physical address in the data storage region, and a controller configured to control the nonvolatile memory. The controller exchanges a first logical address with a second logical address based on a first command and data received from the host device.

Abstract: A mobile telephone (52) comprises a flash memory (3) having a sector data structure. A flash memory (3) has a sector data structure and stores user data (UD) and a firmware (FW) in a sector unit. A user data buffer (4A) and a firmware buffer (4B) are random accessible memories. The buffers (4A) and (4B) store the user data (UD) and firmware (FW) transferred from the memory (3) together with recognition numbers thereof, respectively. As a result of retrieval in the buffer (4B) which is carried out by a CPU (1), when the firmware (FW) required for the execution of an operation input by a user is not present in the buffer (4B), the CPU (1) controls a sequencer (2) to transfer the necessary firmware (FW) from the memory (3) to the buffer (4B). The CPU (1) executes the operational contents by utilizing the firmware (FW) in the buffer (4B). The CPU (1) also utilizes the user data (UD) in the same manner as the firmware (FW).

Abstract: A flash storage medium includes a means which converts logical sector addresses inputted from a predetermined host apparatus to logical cluster addresses constituted by logical sector addresses, to control medium inside based upon a cluster unit constituted by sectors that form an access unit to flash memory. A user block area constituted by flash memory physical blocks corresponding to the logical cluster addresses and an erasing block area constituted by flash memory physical blocks in an erased state are specified in said flash memory. Furthermore, the storage medium includes a means which acquires said physical blocks associated with each other from said logical sector addresses when there is a logical cluster address having two physical blocks associated with each other, and effective and ineffective data are respectively located on these two blocks, and a means which exchanges a physical block between said erasing block area and said user block area.

Abstract: A special memory space access mode enabling common memory space is added to the CF/ATA card access modes, and randomly accessible memory is allocated to the common memory space in this mode. When this special access mode is selected, data stored in the CF/ATA card is transferred to the randomly accessible memory for random access therefrom. This eliminates the need to provide a separate randomly accessible external memory to which card data is transferred for random access in order to randomly access data stored to the CF/ATA card.

Abstract: The 2 lower bits of a medium sector address that the memory device receives from the host system are used as the data corresponding to a column address in a sector in the flash memory. For instance, with the flash memory having the sector capacity of 2048 bytes and the memory device having the sector capacity of 512 bytes, data transfer control portion when the respective 2 lower bits, 00, 01, 10, and 11 are input, starts the data transfer to the flash memory from the buffer memory at a timing corresponding to column addresses 0h, 200h, 400h, and 600h, respectively.

Abstract: The 2 lower bits of a medium sector address that the memory device receives from the host system are used as the data corresponding to a column address in a sector in the flash memory. For instance, with the flash memory having the sector capacity of 2048 bytes and the memory device having the sector capacity of 512 bytes, data transfer control portion when the respective 2 lower bits, 00, 01, 10, and 11 are input, starts the data transfer to the flash memory from the buffer memory at a timing corresponding to column addresses 0h, 200h, 400h, and 600h, respectively.

Abstract: A mobile telephone (52) comprises a flash memory (3) having a sector data structure. A flash memory (3) has a sector data structure and stores user data (UD) and a firmware (FW) in a sector unit. A user data buffer (4A) and a firmware buffer (4B) are random accessible memories. The buffers (4A) and (4B) store the user data (UD) and firmware (FW) transferred from the memory (3) together with recognition numbers thereof, respectively. As a result of retrieval in the buffer (4B) which is carried out by a CPU (1), when the firmware (FW) required for the execution of an operation input by a user is not present in the buffer (4B), the CPU (1) controls a sequencer (2) to transfer the necessary firmware (FW) from the memory (3) to the buffer (4B). The CPU (1) executes the operational contents by utilizing the firmware (FW) in the buffer (4B). The CPU (1) also utilizes the user data (UD) in the same manner as the firmware (FW).

Abstract: A two-valued flash memory (2) and multivalued flash memories (31-33) are mixed in a flash memory group (200) so that management data and user data are stored into the two-valued flash memory (2) and the multivalued flash memories (31-33), respectively. A CPU (4) operates based on universal physical addresses. On the other hand, a two-valued/multivalued selector (7), and a two-valued flash sequencer (6a) and a multivalued flash sequencer (6b) in a flash interface (6) operate based on individual physical addresses so that the management data and the user data to be transmitted/received are divided among the two-valued flash memory (2) and the multivalued flash memories (31-33). This increases storage capacity and transfer rate of a flash storage medium.

Abstract: An IC memory card for use with a host information processing has an interface with the host information processor, a common memory having one or more IC memories and a security circuit for prohibiting access to the common memory if address data input from the host processor does not coincide with preset data. The IC memory card may further provide with an attribute memory which stores a security data and attribute information about the IC card wherein the security circuit checks not only the address data but also the data read out from the attribute memory to enhance the security.

Abstract: An IC memory card having an interface circuit complying with PC card standard and a memory comprises a password check circuit for comparing a password input from an external computer with a predetermined password and one or both of a data decipherment circuit for deciphering enciphered data stored in the memory if the passwords coincide with each other and a data encipherment circuit for enciphering data input from the external computer if the passwords coincide with each other.

Abstract: An IC memory device reduces the time required to complete operations for reading, writing, or erasing data continuously from the same sector address in plural memory chips by accomplishing said operations with a single command and sector address input operation. This IC memory device comprises a data control unit, a command control unit, and a serial clock signal generator. The data control unit handles command and data I/O operations between a data bus and the memory chips. The command control unit generates and applies a chip enable signal to each corresponding memory chip based on externally supplied command data. The serial clock signal generator generates an internal serial clock signal supplied to each memory chip based on an externally supplied serial clock signal. Data can thus be read, written, or erased continuously at the same sector address in plural memory chips with the operating command and sector address being input only once.

Abstract: In a security system apparatus for a memory card used in an information processing apparatus, the memory card has an enciphering control data storing section which stores enciphering control data from which a predetermined password can be obtained by decoding, a main memory section, storing the data from the information processing apparatus, a comparison password storing section which stores a reference password, a password comparison section which compares the reference password with the password from the information processing apparatus, and an access control section for controlling access to main memory section. The information processing apparatus is provided with a data decoding section for decoding the enciphering control data.

Abstract: A memory card includes a volatile memory device, and a power supply supplying an electric voltage to the memory device while the memory card is connected to a host. A timer is started when the memory card is connected to the system. A current detector detects a current flow between a pair of terminals connected to a host. A power supply controller provided between the memory device and the power supply opens repetitively when the current detector does not detect a prescribed current flow before the timer completes a prescribed timing cycle. Thus, the memory card can be accessed only when it is connected to a host having a security function in correspondence to the memory card, while it clears the data stored therein when it is connected to a host which does not correspond to the memory card. Preferably, the current detector is activated by an active signal received from a host.

Abstract: When a connector of a data storage device 10 is connected to a connector 104 of a data processor 100, a power is supplied to a microprocessor 24, and the data storage device 10 sends a discrimination signal to the data processor 100. If the discrimination signal is decided to be a prescribed signal, the data processor 100 sends a detection signal to the data storage device 10. If the detection signal is not received or it is not decided to be a prescribed one, the microprocessor 24 makes a card mode controller 16 inactive to inhibit data read from a memory section 14, and it vanishes the data stored in the memory section 14.

Abstract: An IC card and an IC card system that enable a variety of functions to be added to the IC card. A variety of functions are provided for individual key cards (sub-cards), and the individual key card is detachable from the main body of an IC card so that the addition of and change are easily performed by insertion and change of the individual key card.

Abstract: A data processing system comprises an IC card and a personal computer connected to each other with a connector. The IC card includes a data storage section for storing data, and a control section for controlling the data storage section according to control signals received from the personal computer. When the IC card is connected to the personal computer, the IC card is operated after the personal computer sends an access signal to the IC card. In a modified example, the personal computer sends signals in a prescribed sequence, and the IC card is operated after the IC card detects that the signals are received in a prescribed sequence.