Patents by Inventor Tomoya HIRAISHI

Tomoya HIRAISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile memory device controlling partical usage restriction for memory cell array
    Patent number: 11461044
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell array, first and second storage units, and control unit. The memory cell array includes erase unit areas. The first storage units correspond respectively to the erase unit areas and store items of first information indicating whether a first usage restriction is to be imposed on the corresponding erase unit areas. The second storage units correspond respectively to the erase unit areas and store items of second information indicating whether a second usage restriction is to be imposed on the corresponding erase unit areas. The control unit executes switching control on whether the first usage restriction is to be imposed or not and whether the second usage restriction is to be imposed or not on the memory cell array based on the first and second information.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventor: Tomoya Hiraishi
  • NONVOLATILE MEMORY DEVICE CONTROLLING PARTICAL USAGE RESTRICTION FOR MEMORY CELL ARRAY AND CONTROL METHOD
    Publication number: 20190294368
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell array, first and second storage units, and control unit. The memory cell array includes erase unit areas. The first storage units correspond respectively to the erase unit areas and store items of first information indicating whether a first usage restriction is to be imposed on the corresponding erase unit areas. The second storage units correspond respectively to the erase unit areas and store items of second information indicating whether a second usage restriction is to be imposed on the corresponding erase unit areas. The control unit executes switching control on whether the first usage restriction is to be imposed or not and whether the second usage restriction is to be imposed or not on the memory cell array based on the first and second information.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Tomoya HIRAISHI