Patents by Inventor Tomoya Hirao

Tomoya Hirao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automatic transmission
    Patent number: 10670122
    Abstract: An automatic transmission where the first engagement element is positioned between the continuously variable speed change mechanism and a portion of the second power transmission path on the wheel side, at which the second power transmission path is coupled to the first power transmission path, and is allowed to be switched to the disengaged state for inertial traveling.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 2, 2020
    Assignee: AISIN AW CO., LTD.
    Inventors: Naoki Okoshi, Tomoya Hirao, Masashi Takizawa, Keita Shindo, Kazuya Inaba
  • AUTOMATIC TRANSMISSION
    Publication number: 20180274643
    Abstract: An automatic transmission where the first engagement element is positioned between the continuously variable speed change mechanism and a portion of the second power transmission path on the wheel side, at which the second power transmission path is coupled to the first power transmission path, and is allowed to be switched to the disengaged state for inertial traveling.
    Type: Application
    Filed: October 25, 2016
    Publication date: September 27, 2018
    Applicant: AISIN AW CO., LTD.
    Inventors: Naoki OKOSHI, Tomoya HIRAO, Masashi TAKIZAWA, Keita SHINDO, Kazuya INABA
  • Method for co-verifying hardware and software for a semiconductor device
    Patent number: 7155690
    Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: December 26, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Yamashita, Takao Shinsha, Hideaki Fujikake, Toshiaki Kowatari, Tomoya Hirao, Atsushi Ohkuma, Hiroaki Nishi, Michiaki Muraoka
  • Hardware/software co-verification method
    Publication number: 20050149897
    Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
    Type: Application
    Filed: January 30, 2004
    Publication date: July 7, 2005
    Inventors: Hiroyuki Yamashita, Takao Shinsha, Hideaki Fujikake, Toshiaki Kowatari, Tomoya Hirao, Atsushi Ohkuma, Hiroaki Nishi, Michiaki Muraoka