Abstract: A numerical controller includes: a model holding unit that holds a machine model, the machine model being a model that simulates deformation of a mechanical structure accompanying motion of the mechanical structure in axial directions and representing an error amount as an amount of displacement of a tool; a machining error estimation unit that estimates an error direction and the error amount in the error direction on the basis of axis data that is data on drive of a drive mechanism and the machine model, the error direction being a direction in which displacement of the tool occurs among the axial directions; and a correction amount arithmetic unit that selects one or more of the axes subject to correction, and performs arithmetic to find a correction amount used for correction of a command to be output to the drive mechanism for the axis selected.

Abstract: An automatic transmission where the first engagement element is positioned between the continuously variable speed change mechanism and a portion of the second power transmission path on the wheel side, at which the second power transmission path is coupled to the first power transmission path, and is allowed to be switched to the disengaged state for inertial traveling.

Abstract: An automatic transmission where the first engagement element is positioned between the continuously variable speed change mechanism and a portion of the second power transmission path on the wheel side, at which the second power transmission path is coupled to the first power transmission path, and is allowed to be switched to the disengaged state for inertial traveling.

Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

Abstract: A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.