Abstract: A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Abstract: A memory system includes a memory device including memory chips and a controller. The controller includes first processors configured to perform first processing of network packets in at least one of a network layer and a transport layer of a network protocol, and second processors configured to perform second processing with respect to the memory chips. The controller is configured to extract tag information from a header of a network packet, select one of the first processors associated with a first memory chip that is identified based on the tag information, and control the selected one of the first processors to perform the first processing with respect to the network packet, which causes one of the second processors associated with the first memory chip to perform the second processing based on a payload of the network packet.

Abstract: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Abstract: A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.

Abstract: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.

Abstract: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.

Abstract: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.

Abstract: A semiconductor device of an embodiment includes first and second couplers, an encoding circuit, and a demodulating circuit. The encoding circuit executes differential Manchester encoding on digital data based on a clock inputted thereto via the first coupler and outputs an encoded data. The demodulating circuit includes a first sampling circuit which samples the encoded data inputted via the second coupler based on a sampling frequency set to be two times higher than that of the encoded data and which outputs first sample data, a second sampling circuit which samples the encoded data at a timing earlier than that in the first sampling circuit and which outputs second sample data, a determination circuit which determines whether or not the first and the second sample data match each other, and a selection circuit which selects first phase data or second phase data from the first sample data.

Abstract: A controller can perform a first write process, in which the controller confirms a state of a buffer memory in response to a first interrupt signal, and if the buffer memory has a free space where next transmission data can be written, writes the next transmission data in the buffer memory. Further, the controller can perform a second write process, in which the controller confirms the state of the buffer memory in response to completion of the first write process, and if the buffer memory has the free space, writes the next transmission data in the buffer memory. The controller performs a new one of the first write process after having performed write of the transmission data in the second write process.

Abstract: According to one embodiment, a wireless communication apparatus includes a determination unit, a first setting unit, a second setting unit and a wireless unit. The determination unit determines whether a signal degradation degree is higher than a threshold value. The first setting unit sets first parameters relating to a first data rate and a first communication robustness. The second setting unit sets second parameters relating to a second data rate and a second communication robustness if an instruction signal is received and if the signal degradation degree is higher than the threshold value. The wireless unit communicates with a communication partner using one of the first parameters and the second parameters.

Abstract: The present communication system has a communication terminal (100) and a communication terminal (200) that are respectively provided with a memory for writing and reading using error correction coding/decoding. The communication terminal (100) transmits data to the communication terminal (200) in a high speed mode or normal mode. In high speed mode, the communication terminal (100) reads coded data written in a first memory (112) and transmits the coded data to the communication terminal (200) without decoding. The receiving-side communication terminal (200) writes the received data in a second memory (212) without coding, and decodes the data when said data is read.

Abstract: According to one embodiment, a communication device includes a data storage device and following units. The reception unit receives data from another communication device. The data storage device includes a data area controlled by a file system and a temporary area beyond control of the file system. The processing unit operates in one of first and second start modes, the processing unit being started faster in the second start mode than in the first start mode. The processing unit operating in the second start mode writes the received data to the temporary area, copies the received data in the temporary area to the data area after completion of data reception, and erases the received data in the temporary area after copying.

Abstract: According to one embodiment, a power transmission and reception system includes a power transmitter and a power receiver. The power transmitter includes a power transmission module configured to wireless-transmit power to the power receiver; and a first wireless communication module configured to perform wireless communication of data frame having data with the power receiver. The power receiver includes a power reception module configured to receive the power transmitted from the power transmission module; and a second wireless communication module configured to perform wireless communication of the data frame with the first wireless communication module using the received power. The second wireless communication module is configured to perform wireless communication while the power reception module is not receiving the power.

Abstract: According to an embodiment, a wireless communication device configured to perform an intermittent receiving operation during standby includes a frame detection monitoring unit and a timer unit. The frame detection monitoring unit is configured to monitor detection of a frame during a receiving operation in the intermittent receiving operation. The timer unit is configured to extend a period of the receiving operation when receiving a notice of detection of the frame from the frame detection monitoring unit, and to extend the period of the receiving operation again when receiving again the notice of detection of the frame from the frame detection monitoring unit during an extended period of the receiving operation.

Abstract: According to an embodiment, a wireless communication device includes a first wireless communication section, a wireless power receiving section and a wireless control section. The first wireless communication section is configured to transmit and receive a first wireless signal. The wireless power receiving section is configured to receive power by a second wireless signal. The wireless control section is configured to control the first wireless communication section according to a wireless power reception state of the wireless power receiving section. The wireless control section activates the first wireless communication section after wireless power reception by the wireless power receiving section is started.

Abstract: According to one embodiment, a power transmission and reception system includes a power transmitter and a power receiver. The power transmitter includes: a power transmission module configured to wireless-transmit power to the power receiver; and a first wireless communication module configured to perform wireless communication with the power receiver. The power receiver includes: a power reception module configured to receive the power transmitted from the power transmission module; and a second wireless communication module configured to perform wireless communication with the first wireless communication module using the received power. The second wireless communication module is configured to perform wireless communication while the power reception module is receiving the power.

Abstract: According to one embodiment, a communication device includes a data storage device and following units. The reception unit receives data and information indicating a size of the data. The data storage device includes a data area controlled by a file system and a temporary area beyond control of the file system. The determination unit determines whether the size is not larger than a predetermined threshold value. If it is determined that the size is not larger than the threshold value, the control unit writes the received data to the temporary area, copies the received data in the temporary area to the data area after completion of reception, and erases the received data in the temporary area after copying.

Abstract: A wireless communication device includes a history holder configured to obtain notified timings of transmission requests when the transmission requests are notified, calculates request intervals of notifications of the transmission requests, and holds the request intervals at past n (n is an integer equal to or larger than 2) times; a timing controller configured to determine a transmission interval to the next packet transmission based on the request intervals; a transmitting/receiving unit configured to generate a packet which has time information indicating the transmission interval added to a header part of transmission data, transmits the packet to the other-party wireless communication device, and receives a packet from the other-party wireless communication device; and a communication controller configured to cause at least the transmitting/receiving unit to suspend operation during a period from when the packet is transmitted to when time of the transmission interval elapses.

Abstract: According to one embodiment, a communication apparatus includes a storage unit, a state detecting unit, a communication unit, and a communication control unit. The storage unit configured to store information. The state detecting unit configured to detect, at least one time during an operation of the communication apparatus, whether the storage unit is in a busy state in which no data writing is allowed, or in a ready state in which data writing is allowed. The communication unit configured to perform communication with a destination communication apparatus. The communication control unit configured to control the communication unit to inform the destination communication apparatus that a data receiving operation is stopped for a first time period, if the state detection unit detects that the storage unit has entered the busy state.

Abstract: According to an embodiment, a communication device connected to a host device includes a wireless communication unit and a communication control unit. The communication control unit controls the wireless communication unit to transmit a file which is stored in a storage unit of the communication device by the host device to a transmission destination corresponding to a type of the host device and a type of the communication device using wireless communication.