Patents by Inventor Tomoya IHARA

Tomoya IHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220216116
    Abstract: To provide a new temperature distribution evaluation method, a temperature distribution evaluation device, and a soaking range evaluation method, as the temperature distribution evaluation method which evaluates a temperature distribution of a heating area 40A provided in a heating device 40, the present invention is a temperature distribution evaluation method which, in the heating area 40A, heats a semiconductor substrate 10 and a transmitting and receiving body 20 for transporting a raw material to and from the semiconductor substrate 10, and evaluates a temperature distribution of the heating area 40A on the basis of a substrate thickness variation amount A of the semiconductor substrate 10. Accordingly, temperature distribution evaluation can be implemented for a high temperature area at 1600-2200° C. or the like at which it is hard to evaluate the temperature distribution due to the limit of a thermocouple material.
    Type: Application
    Filed: April 24, 2020
    Publication date: July 7, 2022
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Koji ASHIDA, Tomoya IHARA
  • Publication number: 20210398807
    Abstract: An object of the present invention is to provide a SiC semiconductor substrate capable of reducing a density of basal plane dislocations (BPD) in a growth layer, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a strained layer removal process S10 that removes a strained layer introduced on a surface of a SiC substrate; and an epitaxial growth process S20 that conducts growth under a condition that a terrace width W of the SiC substrate is increased. When a SiC semiconductor substrate is manufactured in such processes, the basal plane dislocations BPD in the growth layer can be reduced, and a yield of a SiC semiconductor device can be improved.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 23, 2021
    Inventors: Tadaaki KANEKO, Koji ASHIDA, Tomoya IHARA, Daichi DOJIMA
  • Publication number: 20210399095
    Abstract: An object of the present invention is to provide a SiC semiconductor substrate having a growth layer with a controlled step height, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a growth process that grows a SiC substrate 10 in a SiC—Si equilibrium vapor pressure environment. In this way, when the SiC substrate 10 is grown in the SiC—Si equilibrium vapor pressure environment, it is possible to provide a SiC semiconductor substrate in which the step height of the growth layer is controlled.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 23, 2021
    Inventors: Tadaaki KANEKO, Koji ASHIDA, Tomoya IHARA, Daichi DOJIMA