Abstract: A comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal.

Abstract: A digital-to-analog conversion circuit includes first current sources weighted depending on lower-order bits of digital input signals and supplied with a first bias voltage and second current sources weighted depending on higher-order bits of the digital input signals and supplied with a second bias voltage. A reference current source circuit generates the first and second bias voltages based on a first reference current. An output circuit combines currents from the first and second current sources in accordance with the digital input signals to generate an output current, the currents from the first and second current sources being set according to the first reference current. A correction circuit changes the first reference current into a second reference current smaller than the first reference current, and adjusts the first and second bias voltages based on currents from the first and second current sources changed according to the second reference current.

Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at ¼ or ¾ of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

Abstract: An SAR analog-to-digital conversion circuit includes: first and second CDACs; first to third comparators respectively comparing outputs of the first and second CDACs, output levels of the first and third CDACs with a reference level; an arithmetic operation circuit; and an SAR control circuit, wherein the SAR control circuit: at each step, determines in which of four ranges output levels of the sampled and held signals of the first and second CDACs are included, the four ranges corresponding to the conversion range being quartered, determines two bits of the digital data and adjusts the output levels of the first and second CDACs so that a level at 1/4 or 3/4 of the voltage range agrees with the intermediate level, and controls first and second switches so that the voltage range is set to be a conversion range at a next step.

Abstract: A comparator includes a first comparison unit configured to compare an input signal with a first signal and a second comparison unit configured to compare the input signal with a second signal having a voltage value lower than a voltage value of the first signal in a case where a voltage value of the input signal is lower than the voltage value of the first signal and compare the input signal with a third signal having a voltage value higher than a voltage value of the first signal in a case where a voltage value of the input signal is higher than the voltage value of the first signal.

Abstract: A first conversion circuit converts a first clock signal based on a signal level of a first voltage into a second clock signal based on a signal level of a second voltage. A flip-flop circuit supplied with the first voltage as an operation voltage latches and outputs a signal, which is based on the signal level of the first voltage, in accordance with the first clock signal. A second conversion circuit supplied with the second voltage as an operation voltage converts a signal level of an input signal, which is based on an output signal of the flip-flop circuit, into the signal level of the second voltage in synchronization with the second clock signal.

Abstract: A first conversion circuit converts a first clock signal based on a signal level of a first voltage into a second clock signal based on a signal level of a second voltage. A flip-flop circuit supplied with the first voltage as an operation voltage latches and outputs a signal, which is based on the signal level of the first voltage, in accordance with the first clock signal. A second conversion circuit supplied with the second voltage as an operation voltage converts a signal level of an input signal, which is based on an output signal of the flip-flop circuit, into the signal level of the second voltage in synchronization with the second clock signal.