Patents by Inventor Tomoya Katou

Tomoya Katou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thin film transistor substrate and process for producing the same
    Patent number: 6512270
    Abstract: A polycrystalline Si thin film transistor substrate having a self-aligned LDD and provided with a gate made of a Mo—W alloy having a W concentration not lower than 5% by weight and lower than 25% by weight and preferably a W concentration of 17 to 22% by weight, which is formed by a process comprising a wet-etching step using an etching solution having a phosphoric acid concentration of 60% to 70% by weight, has uniform characteristic properties and is excellent in productivity.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: January 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Satou, Takuya Takahashi, Tomoya Katou, Toshiki Kaneko, Hajime Ikeda
  • Thin film transistor substrate and process for producing the same
    Publication number: 20020125533
    Abstract: A polycrystalline Si thin film transistor substrate having a self-aligned LDD and provided with a gate made of a Mo—W alloy having a W concentration not lower than 5% by weight and lower than 25% by weight and preferably a W concentration of 17 to 22% by weight, which is formed by a process comprising a wet-etching step using an etching solution having a phosphoric acid concentration of 60% to 70% by weight, has uniform characteristic properties and is excellent in productivity.
    Type: Application
    Filed: August 20, 2001
    Publication date: September 12, 2002
    Inventors: Takeshi Satou, Takuya Takahashi, Tomoya Katou, Toshiki Kaneko, Hajime Ikeda