Abstract: A nonvolatile semiconductor memory cell includes four ferroelectric capacitors and six N channel MOS transistors. When data is to be written or read to or from a certain ferroelectric capacitor, corresponding two word lines are activated.

Abstract: A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

Abstract: A semiconductor memory device includes a plurality of memory cells, a plurality of address detecting circuits capable of registering a defective address indicating a defective memory cell out of the plurality of memory cells for detecting whether an external address matches the defective address or not and each corresponding to 1 bit of the external address or complementary 1 bit thereof, and first and second terminals. Each of the address detecting circuits includes first and second capacitors each having a floating electrode formed of the same layer as a cell plate electrode of a memory cell, a fixed electrode formed of the same layer as a storage node electrode of the memory cell, and a dielectric layer formed of the same layer as a dielectric layer of the memory cell and formed between the floating electrode and the fixed electrode. If 2.times.Vcc is applied to the first terminal and 2.times.Vcc+.delta. is applied to the second terminal, charges are charged in the first and the second capacitors.

Abstract: A defective bit address registering circuit stores an address corresponding to a detective memory cell replaced with a redundant memory cell in a non-volatile manner, and activates a redundant memory cell selection signal S2 if an internal address signal A0, . . . , An, /A0, . . . , /An matches a defective bit address. An I/O data inverting circuit receives input data and output data and outputs the received data without inversion if the redundant memory cell selection signal S2 is inactive. On the other hand, the I/O data inverting circuit outputs inverted data of the received data if the redundant memory cell selection signal S2 is active. Accordingly, if a read operation is performed when data in all the memory cells are at an "L" level such as right after the power supply is turned on, a signal at an "H" level is output only when a memory cell corresponding to a defective bit address is accessed.

Abstract: A DRAM includes an address registration circuit for registering an address of a row including a memory cell having poor data retention characteristic, and an entire refresh period setting circuit for setting a multiple value m of a refreshing period. The row of the registered address is refreshed in the refresh period, and other rows are refreshed in a period m times the refreshing period. Therefore, as compared with the prior art in which all the rows are refreshed in the refresh period set for the rows including the memory cell having poor data retention characteristic, power consumption can be reduced. Further, as compared with another prior art in which the refresh period setting circuit is provided for each row, the number of circuits can be reduced.

Abstract: A semiconductor device having an alignment mark which is improved to enable accurate recognition of the alignment mark is provided. A first interconnection layer is provided on a semiconductor substrate. A second interconnection layer is provided on an interlayer insulating film so that first and second interconnection layers cross each other with interlayer insulating film therebetween. A surface of second interconnection layer includes, in a region where first and second interconnection layers cross each other, a flat portion which reflects laser beam vertically and upwardly and a portion including concaves and convexes which reflects laser beam irregularly, which together form an alignment mark.