Abstract: According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The column includes a semiconductor channel, a charge storage film, and a doped silicon layer. The semiconductor channel extends in the stacking direction. The semiconductor channel is a polycrystalline. An average grain size of crystals in a polycrystalline is not less than a film thickness of the semiconductor channel. The charge storage film is provided between the semiconductor channel and the electrode layers. The doped silicon layer contains a metal element and an impurity other than a metal element. The doped silicon layer is in contact with a top end of the semiconductor channel.

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor substrate; a first semiconductor layer extending in the first direction; and a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer, the first semiconductor layer and the memory layer having a gap, between one of the first insulating layers and the first semiconductor layer, and the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers and the first semiconductor layer.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The semiconductor layer comprises: a first portion extending in the first direction and facing a plurality of the control gate electrodes; and a second portion provided on a closer side to the substrate than this first portion. A film thickness of the first portion in the second direction is larger than a film thickness of the second portion in the second direction. A crystal grain included in the first portion is larger than a crystal grain included in the second portion.

Abstract: In a write operation to memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value, apply a program voltage to a word line corresponding to a selected memory cell, and cause a voltage applied to a first word line corresponding to a first non-selected memory cell positioned between the first end and the selected memory cell to be higher than a voltage applied to a second word line corresponding to a second non-selected memory cell positioned between the second end and the selected memory cell.

Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrata; a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor substrate; a first semiconductor layer extending in the first direction; and a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer, the first semiconductor layer and the memory layer having a gap, between one of the first insulating layers and the first semiconductor layer, and the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers and the first semiconductor layer.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The semiconductor layer comprises: a first portion extending in the first direction and facing a plurality of the control gate electrodes; and a second portion provided on a closer side to the substrate than this first portion. A film thickness of the first portion in the second direction is larger than a film thickness of the second portion in the second direction. A crystal grain included in the first portion is larger than a crystal grain included in the second portion.

Abstract: This power transmission device is connected between an AC wiring system connected to an AC power supply, and a DC power supply, and transmits power from the DC power supply to the AC wiring system. The power transmission device includes an AC power supply voltage signal generator, a power converter, a DC voltage conversion unit, a switching element, and a switch open/close signal generator. The switch open/close signal generator includes: a control signal generation unit to generate a control signal formed from a pulse signal; and a pulse width determination unit to receive the control signal and generate a delayed signal obtained by delaying rising of the control signal, and when the delayed signal becomes a value corresponding to a magnitude of voltage of the AC power supply voltage signal, cause the control signal to fall, thereby making the control signal into the switch open/close signal.

Abstract: A connection member is provided that can be fabricated at low cost and easily attached to a target component. The connection member is a member to be connected to and to communicate with a first component. The connection member is further connectable to another connection member to be connected to and to communicate with a second component. The connection member includes a communicating portion connectable to and communicatable with the first component, engaging portions engageable into the other connection member, and engaged portions into which the other connection member is engageable. These connection members are mutually connectable to communicate with each other.

Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The column includes a semiconductor channel, a charge storage film, and a doped silicon layer. The semiconductor channel extends in the stacking direction. The semiconductor channel is a polycrystalline. An average grain size of crystals in a polycrystalline is not less than a film thickness of the semiconductor channel. The charge storage film is provided between the semiconductor channel and the electrode layers. The doped silicon layer contains a metal element and an impurity other than a metal element. The doped silicon layer is in contact with a top end of the semiconductor channel.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a first stacked portion on a conductive layer, the first stacked portion including a plurality of first layers and a plurality of second layers; forming a first slit; forming a sacrificial film in the first slit; forming a second stacked portion on the first stacked portion and the sacrificial film; forming a second slit; removing the sacrificial film; embedding a separation film; forming a select gate; forming a hole; forming a film including a charge storage film, on an inner wall of the hole; and forming a channel body on an inner side of the film including the charge storage film. The second stacked portion includes the plurality of first layers and the plurality of second layers, the first layers is separately stacked each other, the second layers is provided between the first layers.

Abstract: A connection member is provided that can be fabricated at low cost and easily attached to a target component. The connection member is a member to be connected to and to communicate with a first component. The connection member is further connectable to another connection member to be connected to and to communicate with a second component. The connection member includes a communicating portion connectable to and communicatable with the first component, engaging portions engageable into the other connection member, and engaged portions into which the other connection member is engageable. These connection members are mutually connectable to communicate with each other.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer, a first conductive layer, a second conductive layer, an insulating layer, a block insulating layer formed on an inner surface of a pair of through holes formed in the insulating layer, the second conductive layer, and the first conductive layer, and on an inner surface of a connecting hole formed in the first layer and configured, a charge storage layer formed on the block insulating layer, a tunnel insulating layer formed on the charge storage layer, and a semiconductor pillar formed on the tunnel insulating layer. The semiconductor pillar includes a doped silicide layer which is formed in the insulating layer, a silicon layer formed in the second conductive layer and the first conductive layer, and a silicide layer formed in first layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer, a first conductive layer, a second conductive layer, an insulating layer, a block insulating layer formed on an inner surface of a pair of through holes formed in the insulating layer, the second conductive layer, and the first conductive layer, and on an inner surface of a connecting hole formed in the first layer and configured, a charge storage layer formed on the block insulating layer, a tunnel insulating layer formed on the charge storage layer, and a semiconductor pillar formed on the tunnel insulating layer. The semiconductor pillar includes a doped silicide layer which is formed in the insulating layer, a silicon layer formed in the second conductive layer and the first conductive layer, and a silicide layer formed in first layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer.

Abstract: According to one embodiment, a first electrode, a second electrode, and a variable resistance layer are provided. The variable resistance layer is arranged between the first electrode and the second electrode and contains a polycrystalline semiconductor as a main component.

Abstract: A pedal reaction force control device is preferably used for performing a control of applying a pedal reaction force to a pedal. A pedal reaction force control unit performs a control of the pedal reaction force so that a constant acceleration feeling is gained by a constant pedal pressure, with respect to a change of vehicle speed. Namely, the pedal reaction force control unit performs the control so that the pedal reaction force which realizes the constant acceleration feeling becomes constant. Therefore, when a driver presses on the pedal by the constant pedal pressure in order to accelerate a vehicle, it becomes possible to appropriately realize such an acceleration that the constant acceleration feeling is gained. Thereby, it is possible to realize a feeling without decreasing an acceleration feeling.

Abstract: A required torque waveform, a target torque waveform, and a maximum torque that can be realized/achieved by hardware are updated at time t2. When a required torque value at time t2 exceeds the maximum torque, the time at which the target torque waveform is realized is delayed until time tb at which this required torque value matches the maximum torque.