Patents by Inventor Tomoya Oori

Tomoya Oori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230402314
    Abstract: A method for manufacturing a semiconductor device includes: forming a mask film such that it covers part of a first trench, thereby dividing the first trench in the longitudinal direction to form one or more second trenches; filling a first insulating film into the second trenches; removing the mask film; and forming a second insulating film such that it covers the entire first trench.
    Type: Application
    Filed: February 24, 2023
    Publication date: December 14, 2023
    Applicant: Kioxia Corporation
    Inventor: Tomoya OORI
  • Publication number: 20190371635
    Abstract: According to one embodiment, the plasma processing apparatus includes a support table configured to support a substrate, an edge ring provided at an outer periphery of the support table on a side with a mounting surface for placing the substrate thereon, a transfer arm configured to transfer the substrate onto the support table, a sensor configured to detect a position of the edge ring, a drive part configured to drive the transfer arm, and a controller configured to control the drive part. The controller is configured to calculate an offset amount between a center position of the edge ring and a center position of the substrate under transfer by the transfer arm, on a basis of information output from the sensor, and correct a movement amount of the transfer arm by using the offset amount.
    Type: Application
    Filed: February 11, 2019
    Publication date: December 5, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Tomoya OORI
  • Patent number: 10325920
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chihiro Abe, Keisuke Kikutani, Katsumi Yamamoto, Tomoya Oori
  • Publication number: 20170330890
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Application
    Filed: November 14, 2016
    Publication date: November 16, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Chihiro ABE, Keisuke KlKUTANI, Katsumi YAMAMOTO, Tomoya OORI
  • Publication number: 20160313644
    Abstract: According to one embodiment, at first, a first resist film made from a first radiation sensitive composition is formed on a processing object film. Then, light exposure and development to the first resist film are performed to form a first resist pattern. Thereafter, an insolubilization process to insolubilize the first resist pattern to a solvent of a second radiation sensitive composition is performed. Then, a second resist film made from the second radiation sensitive composition is formed on the first resist pattern. Then, light exposure and development to the second resist film are performed to form a second resist pattern. At least one of the first radiation sensitive composition and the second radiation sensitive composition is made of a polymer compound resistant to oxygen that is present at the time of plasma etching.
    Type: Application
    Filed: August 28, 2015
    Publication date: October 27, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoya OORI, Takehiro KONDOH, Naoya KANEDA, Eiichi SODA
  • Publication number: 20160247815
    Abstract: According to one embodiment, it includes a stacked body formed such that a first layer and a second layer, which are made of materials different from each other, are alternately stacked, and one of layers of the first layer or one of layers of the second layer is replaced with a third layer that does not transmit light of a wavelength ?, and an opening that penetrates the stacked body in a stack direction and has a diameter or width smaller than the wavelength ?.
    Type: Application
    Filed: June 5, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tomoya OORI
  • Publication number: 20140234782
    Abstract: A method for manufacturing a semiconductor device according to an embodiment of the invention includes applying a resist on a substrate surface in a resist application apparatus, light-exposing the resist on the substrate surface in a light exposure apparatus, and after the light-exposing the resist, developing the resist in a development apparatus. The resist is a negative resist. The developing the resist includes mounting the substrate on a support stage including a rotating mechanism of the development apparatus, after the mounting the substrate on the support stage, developing the resist, after the mounting the substrate on the support stage, removing the resist on a peripheral edge of the substrate, and after the developing the resist, and after the removing the resist on the peripheral edge of the substrate, dismounting the substrate from the support stage.
    Type: Application
    Filed: July 9, 2013
    Publication date: August 21, 2014
    Inventor: Tomoya OORI
  • Patent number: 8765362
    Abstract: According to one embodiment, a patterning method includes exposure-transferring a plurality of first island pattern images and a plurality of second island pattern images onto a resist film, each of the plurality of first island pattern images having a configuration having a contour line or a major axis extending in a third direction, the plurality of first island pattern images having a staggered arrangement, each of the plurality of second island pattern images having a configuration having a contour line or a major axis extending in a fourth direction, the plurality of second island pattern images having a staggered arrangement, the first island pattern images and the second island pattern images being continuous in the first direction by a portion of each of the second island pattern images overlapping one of the first island pattern images.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoya Oori
  • Patent number: 8747682
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes forming a plurality of regions on a foundation and the plurality of the regions correspond to different pattern sizes. The method includes separating each of a plurality of block copolymers from another one of the plurality of the block copolymers and segregating the each of the plurality of the block copolymers into a corresponding one of the regions. The method includes performing a phase separation of the each of the block copolymers of each of the regions. The method includes selectively removing a designated phase of each of the phase-separated block copolymers to form a pattern of the each of the block copolymers and the pattern has a different pattern size for the each of the regions.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara, Yukiko Sato, Yoshihisa Kawamura
  • Publication number: 20140065556
    Abstract: According to one embodiment, a patterning method includes exposure-transferring a plurality of first island pattern images and a plurality of second island pattern images onto a resist film, each of the plurality of first island pattern images having a configuration having a contour line or a major axis extending in a third direction, the plurality of first island pattern images having a staggered arrangement, each of the plurality of second island pattern images having a configuration having a contour line or a major axis extending in a fourth direction, the plurality of second island pattern images having a staggered arrangement, the first island pattern images and the second island pattern images being continuous in the first direction by a portion of each of the second island pattern images overlapping one of the first island pattern images.
    Type: Application
    Filed: December 19, 2012
    Publication date: March 6, 2014
    Inventor: Tomoya OORI
  • Publication number: 20120322273
    Abstract: A coating film forming method according to an embodiment, includes rotating a substrate, supplying a chemical solution for forming a coating film onto the rotating substrate, and supplying a liquid having a lower temperature than an atmosphere of the substrate to an edge of the substrate from a back side of the substrate while a film is formed by supplying the chemical solution onto the rotating substrate.
    Type: Application
    Filed: January 25, 2012
    Publication date: December 20, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tomoya OORI
  • Patent number: 8329385
    Abstract: A method of manufacturing a semiconductor device according to one embodiment, includes: forming a first mask material film on a workpiece film formed on a semiconductor substrate; forming a resist pattern on the first mask material film; forming a second mask material film having a desired film thickness on the first mask material film so as to cover the resist pattern; carrying out etchback of the second mask material film so as to expose the resist pattern and the first mask material film; processing the resist pattern and the first mask material film simultaneously which are exposed, while leaving the second mask material film of which etchback is carried out; and processing the workpiece film which exposes under the first mask material film.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eishi Shiobara, Keisuke Kikutani, Kazuyuki Yahiro, Kentaro Matsunaga, Tomoya Oori
  • Patent number: 8158332
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a first resist pattern made of a first resist material on a workpiece material; irradiating an energy beam onto the first resist pattern, the energy beam exposing the first resist material to light; performing a treatment for improving resistance the first resist pattern after irradiation of the energy beam; forming a coating film on the workpiece material so as to cover the first resist pattern; and forming a second resist pattern made of a second resist material on the coating film after the treatment.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Tomoya Oori, Eishi Shiobara
  • Patent number: 8138059
    Abstract: A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mask material onto the foundation film so as to cover the core pattern, the mask material being crosslinkable upon supply acid from the core pattern; etching back the mask material to expose an upper surface of the core pattern and remove a portion of the mask material formed on the end portion of the core pattern, thereby leaving a mask material side wall portion formed on a side wall of the core pattern; and removing the core pattern and processing the foundation film by using the mask material sidewall portion left on the foundation film as a mask.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: March 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Hirokazu Kato, Tomoya Oori
  • Publication number: 20110086313
    Abstract: In one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can forms a resist film on a substrate. The method can expose a portion of the resist film. The portion is formed on a device area of the substrate and the device area includes a center portion of the substrate. After the exposing the device area, the method can apply a reaction control process for controlling expansion of a reacted region in the resist film. After the applying the reaction control process, the method can expose another portion of the resist film and the another portion is formed on a peripheral area surrounding the device area. After the exposing the peripheral area, the method can heat the resist film, and after the heating, the method can develop the resist film.
    Type: Application
    Filed: June 25, 2010
    Publication date: April 14, 2011
    Inventors: Tomoya OORI, Shinichi ITO
  • Publication number: 20110034029
    Abstract: According to one embodiment, a pattern formation method is disclosed. The method includes forming a plurality of regions on a foundation and the plurality of the regions correspond to different pattern sizes. The method includes separating each of a plurality of block copolymers from another one of the plurality of the block copolymers and segregating the each of the plurality of the block copolymers into a corresponding one of the regions. The method includes performing a phase separation of the each of the block copolymers of each of the regions. The method includes selectively removing a designated phase of each of the phase-separated block copolymers to form a pattern of the each of the block copolymers and the pattern has a different pattern size for the each of the regions.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 10, 2011
    Inventors: Kentaro MATSUNAGA, Tomoya Oori, Eishi Shiobara, Yukiko Sato, Yoshihisa Kawamura
  • Publication number: 20100183982
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a first resist pattern made of a first resist material on a workpiece material; irradiating an energy beam onto the first resist pattern, the energy beam exposing the first resist material to light; performing a treatment for improving resistance the first resist pattern after irradiation of the energy beam; forming a coating film on the workpiece material so as to cover the first resist pattern; and forming a second resist pattern made of a second resist material on the coating film after the treatment.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 22, 2010
    Inventors: Kentaro MATSUNAGA, Tomoya Oori, Eishi Shiobara
  • Publication number: 20100120255
    Abstract: A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mask material onto the foundation film so as to cover the core pattern, the mask material being crosslinkable upon supply acid from the core pattern; etching back the mask material to expose an upper surface of the core pattern and remove a portion of the mask material formed on the end portion of the core pattern, thereby leaving a mask material side wall portion formed on a side wall of the core pattern; and removing the core pattern and processing the foundation film by using the mask material sidewall portion left on the foundation film as a mask.
    Type: Application
    Filed: September 22, 2009
    Publication date: May 13, 2010
    Inventors: Kentaro MATSUNGA, Hirokazu Kato, Tomoya Oori
  • Publication number: 20090305166
    Abstract: A method of manufacturing a semiconductor device according to one embodiment, includes: forming a first mask material film on a workpiece film formed on a semiconductor substrate; forming a resist pattern on the first mask material film; forming a second mask material film having a desired film thickness on the first mask material film so as to cover the resist pattern; carrying out etchback of the second mask material film so as to expose the resist pattern and the first mask material film; processing the resist pattern and the first mask material film simultaneously which are exposed, while leaving the second mask material film of which etchback is carried out; and processing the workpiece film which exposes under the first mask material film.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 10, 2009
    Inventors: Eishi SHIOBARA, Keisuke Kikutani, Kazuyuki Yahiro, Kentaro Matsunaga, Tomoya Oori