Patents by Inventor Tomoya Sanuki
Tomoya Sanuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11222900Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.Type: GrantFiled: December 21, 2018Date of Patent: January 11, 2022Assignee: Toshiba Memory CorporationInventors: Yoshiro Shimojo, Tomoya Sanuki
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Publication number: 20210366879Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Toshiba Memory CorporationInventor: Tomoya SANUKI
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Publication number: 20210296298Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.Type: ApplicationFiled: August 28, 2020Publication date: September 23, 2021Inventors: Tomoya SANUKI, Keisuke NAKATSUKA, Hiroshi MAEJIMA, Kenichiro YOSHII, Takashi MAEDA, Hideo WADA
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Patent number: 11127717Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.Type: GrantFiled: September 5, 2019Date of Patent: September 21, 2021Assignee: Toshiba Memory CorporationInventor: Tomoya Sanuki
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Publication number: 20210272946Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.Type: ApplicationFiled: August 28, 2020Publication date: September 2, 2021Inventors: Tomoya SANUKI, Toshio FUJISAWA, Hiroshi MAEJIMA, Takashi MAEDA
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Publication number: 20210149568Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.Type: ApplicationFiled: December 14, 2020Publication date: May 20, 2021Applicant: Kioxia CorporationInventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
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Publication number: 20210118898Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Applicant: Toshiba Memory CorporationInventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
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Publication number: 20210090616Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Applicant: Toshiba Memory CorporationInventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
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Publication number: 20210082879Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.Type: ApplicationFiled: March 2, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Tomoya SANUKI, Hiroshi MAEJIMA, Tetsuaki UTSUMI
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Publication number: 20210082880Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.Type: ApplicationFiled: March 5, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Tomoya Sanuki, Masayoshi Tagami
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Publication number: 20210074638Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.Type: ApplicationFiled: September 9, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Tomoya SANUKI, Keisuke NAKATSUKA, Yasuhito YOSHIMIZU
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Patent number: 10892269Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.Type: GrantFiled: May 10, 2019Date of Patent: January 12, 2021Assignee: Toshiba Memory CorporationInventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
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Patent number: 10872900Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.Type: GrantFiled: February 22, 2019Date of Patent: December 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoya Sanuki, Yusuke Higashi, Hideto Horii, Masaki Kondo, Hiroki Tokuhira, Hideaki Aochi
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Patent number: 10867641Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: GrantFiled: March 18, 2019Date of Patent: December 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Keisuke Nakatsuka, Tomoya Sanuki, Takashi Maeda, Go Shikata, Hideaki Aochi
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Publication number: 20200286842Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.Type: ApplicationFiled: September 5, 2019Publication date: September 10, 2020Applicant: Toshiba Memory CorporationInventor: Tomoya SANUKI
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Publication number: 20200279841Abstract: According to one embodiment, a semiconductor device includes a first substrate and a logic circuit provided on the first substrate. The device further includes a memory cell provided above the logic circuit and a second substrate provided above the memory cell. The device further includes a bonding pad provided above the second substrate and electrically connected to the logic circuit. The device further includes a wiring that is provided above the second substrate, is electrically connected to the memory cell, and includes at least one of a data signal line, a control voltage line, and a power supply line.Type: ApplicationFiled: August 23, 2019Publication date: September 3, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Tomoya SANUKI
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Publication number: 20200091238Abstract: According to one embodiment, a storage device includes a first conductor extending along a first direction, first variable-resistance elements on the first conductor, and a second conductor on the first variable-resistance elements and extending along a second direction. A plurality of second variable-resistance elements is on the second conductor. A third conductor is on the plurality of second variable-resistance elements. The third conductor extends along the first direction. A first switching element is connected between the second conductor and a corresponding one of the first variable-resistance elements. A second switching element is connected between the third conductor and a corresponding one of second variable-resistance elements.Type: ApplicationFiled: February 26, 2019Publication date: March 19, 2020Inventor: Tomoya SANUKI
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Publication number: 20200091174Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.Type: ApplicationFiled: February 22, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Tomoya SANUKI, Yusuke HIGASHI, Hideto HORII, Masaki KONDO, Hiroki TOKUHIRA, Hideaki AOCHI
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Publication number: 20200090710Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.Type: ApplicationFiled: March 18, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
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Publication number: 20200043942Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.Type: ApplicationFiled: December 21, 2018Publication date: February 6, 2020Applicant: Toshiba Memory CorporationInventors: Yoshiro SHIMOJO, Tomoya Sanuki