Patents by Inventor Tomoya Taguchi

Tomoya Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250235784
    Abstract: Provided are a program, an information processing system, and an information processing method that serve to improve convenience concerning experience of game rendition. The following units are included: a raising-function providing unit that provides a raising function for presenting selection candidates for instructing an action of a game medium being raised among the game media, determining a rendition execution pattern on the basis of a condition associated with an action selected by the player, and executing game rendition; and a rendition-viewing-function providing unit that provides a rendition viewing function for letting the player select the game medium and the rendition execution pattern and for executing the game rendition on the basis of the results of selection. The rendition-viewing-function providing unit presents the rendition execution patterns randomly determined with the raising function as selection candidates, allowing the player to arbitrarily select the rendition execution pattern.
    Type: Application
    Filed: April 9, 2025
    Publication date: July 24, 2025
    Applicant: CYGAMES, INC.
    Inventors: Tomoya Taguchi, Yuki Tomizawa, Seiya Kamizato, Naoyuki Takahashi
  • Patent number: 12272701
    Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: April 8, 2025
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Publication number: 20240397602
    Abstract: A vacuum tube support structure includes a vacuum tube, a cover configured to cover the vacuum tube, and a support member configured to support the vacuum tube and the cover. The cover includes a fluid introduction port configured to allow a fluid to pass through the cover to introduce the fluid inside the cover and a fluid discharge port configured to allow the fluid to pass through the cover to discharge the fluid from inside the cover. The fluid introduced through the fluid introduction port contacts the vacuum tube and is discharged through the fluid discharge port.
    Type: Application
    Filed: May 6, 2024
    Publication date: November 28, 2024
    Applicant: Yokogawa Electric Corporation
    Inventors: Tomoya Taguchi, Kazuki Setsuda
  • Publication number: 20240304650
    Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions constituting pn junctions with the first semiconductor region. The semiconductor substrate includes the plurality of second semiconductor in a side of the second main surface. Each of the plurality of second semiconductor regions includes a first region including a textured surface, and a second region including no textured surface. A thickness of the first region at a deepest position of recesses of the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya TAGUCHI, Yuki Yoshida, Katsumi Shibayama
  • Publication number: 20240293753
    Abstract: A non-transitory computer readable medium stores a program causing a computer to execute: processing for storing character information of a character nurtured in a nurturing game, in association with unique information of a player who nurtured the character; processing for, based on an operation by a first player, setting a plurality of characters as a plurality of battle characters, the plurality of battle characters including at least one character nurtured by at least one second player other than the first player; and processing for executing a battle game in which the plurality of battle characters play a battle by using the character information of the plurality of battle characters.
    Type: Application
    Filed: May 7, 2024
    Publication date: September 5, 2024
    Applicant: CYGAMES, INC.
    Inventors: Tomoya Taguchi, Seiya Kamizato, Yuki Nishi, Masaru Kubo, Nozomi Kikuchi, Ikko Suto
  • Patent number: 12017504
    Abstract: A duct structure having excellent sealing performance at a connection portion between a duct and a piping member. The duct structure includes a duct and a piping member. The duct includes an opening in a tubular portion, and the piping member includes a piping portion. The piping portion is inserted into the opening and connected to the duct, and a foam rubber sealing material is disposed in a compressed state between an outer peripheral surface of the piping portion and an edge of the opening.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: June 25, 2024
    Assignees: KYORAKU CO., LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Ryosuke Oki, Tomoya Taguchi
  • Patent number: 12021104
    Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions constituting pn junctions with the first semiconductor region. The semiconductor substrate includes the plurality of second semiconductor in a side of the second main surface. Each of the plurality of second semiconductor regions includes a first region including a textured surface, and a second region including no textured surface. A thickness of the first region at a deepest position of recesses of the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 25, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Publication number: 20230378201
    Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya TAGUCHI, Yuki Yoshida, Katsumi Shibayama
  • Patent number: 11764236
    Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: September 19, 2023
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Publication number: 20230001765
    Abstract: A duct structure having excellent sealing performance at a connection portion between a duct and a piping member. The duct structure includes a duct and a piping member. The duct includes an opening in a tubular portion, and the piping member includes a piping portion. The piping portion is inserted into the opening and connected to the duct, and a foam rubber sealing material is disposed in a compressed state between an outer peripheral surface of the piping portion and an edge of the opening.
    Type: Application
    Filed: January 8, 2021
    Publication date: January 5, 2023
    Applicants: KYORAKU CO., LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Ryosuke OKI, Tomoya TAGUCHI
  • Publication number: 20220367533
    Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya TAGUCHI, Yuki YOSHIDA, Katsumi SHIBAYAMA
  • Patent number: 11450695
    Abstract: A semiconductor substrate including a first main surface and a second main surface opposing each other is provided. The semiconductor substrate includes a first semiconductor region of a first conductivity type. The semiconductor substrate includes a plurality of planned regions where a plurality of second semiconductor regions of a second conductivity type forming pn junctions with the first semiconductor region are going to be formed, in a side of the second main surface. A textured region is formed on surfaces included in the plurality of planned regions, in the second main surface. The plurality of second semiconductor regions are formed in the plurality of planned regions after forming the textured region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: September 20, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Patent number: 11413708
    Abstract: An object cutting method includes: a first step of preparing an object to be processed including a single crystal silicon substrate and a functional device layer provided on a first main surface side and forming an etching protection layer on a second main surface of the object; a second step of irradiating the object with laser light to form at least one row of modified regions in the single crystal silicon substrate and to form a fracture in the object so as to extend between the at least one row of modified regions and a surface of the etching protection layer; and a third step of performing dry etching on the object from the second main surface side, in a state in which the etching protection layer is formed on the second main surface, to form a groove opening to the second main surface.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: August 16, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takeshi Sakamoto, Tomoya Taguchi
  • Patent number: 11367655
    Abstract: A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 21, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Takeshi Sakamoto
  • Patent number: 11276794
    Abstract: A semiconductor substrate includes first and second main surfaces opposing each other. The semiconductor substrate includes second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. The second semiconductor regions are two-dimensionally distributed in a first direction and a second direction orthogonal to each other when viewed in a direction orthogonal to the semiconductor substrate. The first region and the second region are adjacent to each other in a direction crossing the first direction and the second direction. The textured surface of the first region is located toward the first main surface in comparison to the surface of the second region in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 15, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Patent number: 11239266
    Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a plurality of second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. An insulating film includes a first insulating film covering surfaces of the second semiconductor regions, and a second insulating film covering peripheries of pad electrodes. The pad electrodes include a first electrode region in contact with the second region, and a second electrode region continuous with the first electrode region. The second electrode region is disposed on at least a part of a region included in the first insulating film and corresponding to the first region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 1, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya Taguchi, Yuki Yoshida, Katsumi Shibayama
  • Patent number: 11233354
    Abstract: A hermetic terminal (110) includes a barrier wall (12) to be joined to a housing (11), a body (15) that is to be connected to a signal ground and is fixed to the barrier wall (12) via a first insulator (13), and a signal line (16) passing through the body (15) and fixed to the body (15) via a second insulator (14). When the barrier wall (12) is joined to the housing (11), a space (28) is formed between an inner wall of the housing (11) and a surface (31) of the body (15) intersecting an end face (29) of the body (15) positioned towards the inside of the housing (11).
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: January 25, 2022
    Assignee: Yokogawa Electric Corporation
    Inventors: Hideki Fujiwara, Kohei Tomonaga, Yasushi Hyono, Tomoya Taguchi
  • Publication number: 20210159255
    Abstract: A semiconductor substrate includes a first main surface and a second main surface opposing each other. The semiconductor substrate includes a plurality of second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. An insulating film includes a first insulating film covering surfaces of the second semiconductor regions, and a second insulating film covering peripheries of pad electrodes. The pad electrodes include a first electrode region in contact with the second region, and a second electrode region continuous with the first electrode region. The second electrode region is disposed on at least a part of a region included in the first insulating film and corresponding to the first region. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Application
    Filed: April 11, 2019
    Publication date: May 27, 2021
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya TAGUCHI, Yuki YOSHIDA, Katsumi SHIBAYAMA
  • Publication number: 20210159351
    Abstract: A semiconductor substrate includes first and second main surfaces opposing each other. The semiconductor substrate includes second semiconductor regions in a side of the second main surface. Each of the second semiconductor regions includes a first region including a textured surface, and a second region where a bump electrode is disposed. The second semiconductor regions are two-dimensionally distributed in a first direction and a second direction orthogonal to each other when viewed in a direction orthogonal to the semiconductor substrate. The first region and the second region are adjacent to each other in a direction crossing the first direction and the second direction. The textured surface of the first region is located toward the first main surface in comparison to the surface of the second region in a thickness direction of the semiconductor substrate. The first main surface is a light incident surface of the semiconductor substrate.
    Type: Application
    Filed: April 11, 2019
    Publication date: May 27, 2021
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya TAGUCHI, Yuki YOSHIDA, Katsumi SHIBAYAMA
  • Publication number: 20210125868
    Abstract: A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.
    Type: Application
    Filed: February 9, 2018
    Publication date: April 29, 2021
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Tomoya TAGUCHI, Takeshi SAKAMOTO