Abstract: A sample holder includes: a ceramic substrate including a first circular main surface and a second circular main surface, the ceramic substrate including a first layer, a second layer and a third layer located in sequence; a conductive section located between the second layer and the third layer, the conductive section including a portion extending in a circumferential direction of the first circular main surface and a portion extending in a radial direction of the first circular main surface; a first heater located between the first layer and the second layer; and a second heater located between the second layer and the third layer and connected to the conductive section, the second heater having an annular shape which surrounds the first heater and the conductive section when viewed in a transparent plan view of the sample holder.

Abstract: A scan-path circuit is made up of cascaded flip-flops which are input/output circuits of a combinational logic circuit. In a logic circuit 21 which adopts a scan design test technique for simplifying a test of the same by serially shifting a test result through the flip-flops, selectors for directly connecting inputs of the respective flip-flops of the scan-path circuit to a scan input are provided. After causing all flip-flops to have identical values (either “0” or “1”), the values are shifted and outputted so that the location of a failure is specified. With this, the maximum period of time required by the test does not exceed the total of clocks for the shifting through all stages and one more stage. Thus, in addition to the checking of the presence of a failure, the location of a failure is, if necessary, specified in a short period of time.

Abstract: A scan-path circuit is made up of cascaded flip-flops which are input/output circuits of a combinational logic circuit. In a logic circuit 21 which adopts a scan design test technique for simplifying a test of the same by serially shifting a test result through the flip-flops, selectors for directly connecting inputs of the respective flip-flops of the scan-path circuit to a scan input are provided. After causing all flip-flops to have identical values (either “0” or “1”), the values are shifted and outputted so that the location of a failure is specified. With this, the maximum period of time required by the test does not exceed the total of clocks for the shifting through all stages and one more stage. Thus, in addition to the checking of the presence of a failure, the location of a failure is, if necessary, specified in a short period of time.