Abstract: An inventive semiconductor integrated circuit device includes multiple transistor banks over a substrate. The banks are arranged to be substantially parallel to each other in a planar layout of the device. Each said bank includes a plurality of unit transistors, each including a base, an emitter and a collector. In the planar layout of the device, a position of a first one of the transistors is shifted from a position of a second one of the transistors in a direction in which the banks extend. The first and second transistors belong to first and second ones of the banks, respectively, which are adjacent to each other. The second transistor is closer to the first transistor than any other transistor in the second bank.

Abstract: A method for fabricating a compound semiconductor device according to the present invention includes the steps of: a) depositing a first compound semiconductor layer over a substrate; b) depositing a second compound semiconductor layer on the first compound semiconductor layer, the second compound semiconductor layer being made of a compound with etch properties different from those of a compound for the first compound semiconductor layer; c) forming an etching mask on the second compound semiconductor layer, the etching mask having a first opening; d) anisotropically dry-etching the second compound semiconductor layer selectively with respect to the first compound semiconductor layer through the etching mask, thereby forming a second opening in the second compound semiconductor layer; and e) isotropically dry-etching the second compound semiconductor layer selectively with respect to the first compound semiconductor layer through the etching mask, thereby side-etching a side of the second opening and making

Abstract: A WSi film is deposited on a semi-insulative GaAs substrate. Thereafter, a first Al mask and a second SiO.sub.2 mask are formed such that these two masks overlap on the WSi film. A SF.sub.6 /CF.sub.4 mixture, which contains a gas of SF.sub.6 in an amount of more than 20%, is used to dry-etch the WSi film. The WSi film is T-shaped, in other words the WSi film becomes gradually downwardly narrower in lateral length. The second mask is stripped. A .GAMMA.-shaped gate electrode is formed by means of an anisotropic etching process. Subsequently, an isotropic etching process is carried out to reduce the gate length of the electrode down to 0.5 .mu.m or less. Silicon ions are implanted to form individual n' layers. A through film is deposited. Silicon ions are implanted to form individual n.sup.+ layers.

Abstract: A method for producing a field effect transistor includes: a first step of forming an insulating film over a substrate; a second step of dry etching the insulating film to form a rectangular insulating pattern having side surfaces; a third step of forming a gate electrode film over the substrate having the rectangular insulating pattern; a fourth step of conducting substantially anisotropic etching of the gate electrode film to form side walls made of the gate electrode film adjacent to the side surfaces of the rectangular insulating pattern; and a fifth step of removing at least a portion of the insulating pattern to form a side wall gate.

Abstract: A WSi film is deposited on a semi-insulative GaAs substrate. Thereafter, a first Al mask and a second SiO.sub.2 mask are formed such that these two masks overlap on the WSi film. A SF.sub.6 /CF.sub.4 mixture, which contains a gas of SF.sub.6 in an amount of more than 20%, is used to dry-etch the WSi film. The WSi film is T-shaped, in other words the WSi film becomes gradually downwardly narrower in lateral length. The second mask is stripped. A .GAMMA.-shaped gate electrode is formed by means of an anisotropic etching process. Subsequently, an isotropic etching process is carried out to reduce the gate length of the electrode down to 0.5 .mu.m or less. Silicon ions are implanted to form individual n' layers. A through film is deposited. Silicon ions are implanted to form individual n.sup.+ layers.

Abstract: After forming an n-type active layer, an n.sup.+ -type source region and an n.sup.+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain electrodes are formed. By effecting overetching on the silicon nitride film using a resist mask formed on the silicon nitride film, an upper layer portion of the silicon oxide film at a gate electrode formation region is removed, and a carrier concentration at the active layer immediately under the gate electrode is reduced. This improves a gate/drain breakdown voltage. Thereafter, a lower layer portion of the silicon oxide film at the gate formation region is removed by wet etching, and the gate electrode is formed at this removed region. A drain breakdown voltage is improved owing to reduction of the carrier concentration only at the surface region of the active layer immediately under the gate electrode.