Patents by Inventor Tomoyasu EGUCHI

Tomoyasu EGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ceramic electronic device and wiring substrate
    Patent number: 11521798
    Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 6, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hirotaka Ohno, Tomoyasu Eguchi, Kenichi Kitazawa, Ryuichi Shibasaki
  • Ceramic electronic device and wiring substrate
    Patent number: 11488781
    Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: November 1, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hirotaka Ohno, Tomoyasu Eguchi, Kenichi Kitazawa, Ryuichi Shibasaki
  • CERAMIC ELECTRONIC DEVICE AND WIRING SUBSTRATE
    Publication number: 20200194183
    Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).
    Type: Application
    Filed: December 2, 2019
    Publication date: June 18, 2020
    Inventors: Hirotaka OHNO, Tomoyasu EGUCHI, Kenichi KITAZAWA, Ryuichi SHIBASAKI