Abstract: A multilayer ceramic electronic device includes an element body and external electrodes. At least one of the pair of external electrodes includes a first metal layer and a second metal layer. The first metal layer covers a part of internal electrodes and a first portion of cover dielectric layers and side margin sections which is located on a side of the internal electrodes, does not cover a second portion of the cover dielectric layers and the side margin section which is other than the first portion, contacts a part of the internal electrodes, and has a main component of nickel or copper, at a corresponding end face of the element body. The second metal layer covers the first metal layer, contacts at least a part of the second portion on a side of the first metal layer, and has a main component of tin.

Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).

Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).

Abstract: A ceramic electronic device includes: a multilayer chip in which each of internal electrode layers and each of dielectric layers are alternately stacked, wherein the multilayer chip has a first capacity region having a first electrostatic capacity C1 and a first inductance L1 and a second capacity region having a second electrostatic capacity C2 and a second inductance L2, wherein the first electrostatic capacity C1, the first inductance L1, the second electrostatic capacity C2 and the second inductance L2 satisfy (C1·L1)/(C2·L2)<0.5 or 1.9<(C1·L1)/(C2·L2).