Patents by Inventor Tomoyasu TAKAI

Tomoyasu TAKAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9916236
    Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: March 13, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyasu Takai, Tetsuya Kamino, Makoto Kozawa
  • Patent number: 9875177
    Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: January 23, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyasu Takai, Tetsuya Kamino, Makoto Kozawa
  • Publication number: 20150331822
    Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 19, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyasu TAKAI, Tetsuya KAMINO, Makoto KOZAWA
  • Publication number: 20120072779
    Abstract: The memory leak monitoring device for monitoring a memory leak occurring by an executed program reserving a memory area, the memory leak monitoring device comprising a retention period acquisition unit that acquires a retention period of each program indicating an elapsed time after a memory area used by the program is reserved, and a detection unit that detects a program in which a memory leak may occur by comparing the acquired retention period with a reference time.
    Type: Application
    Filed: September 22, 2011
    Publication date: March 22, 2012
    Inventor: Tomoyasu TAKAI