Patents by Inventor Tomoyasu Tate

Tomoyasu Tate has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11483502
    Abstract: An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: October 25, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Wei Deng, Tomoyasu Tate, Rui Wang
  • Patent number: 10469784
    Abstract: The present disclosure relates to a control device, a control method, and a solid-state imaging device that enable a larger number of shutter row addresses to be set at the same time. A vertical selection decoder and a latch circuit set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses. The present disclosure is applicable to, for example, a CMOS image sensor that sets the shutter row addresses.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: November 5, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Tomoyasu Tate
  • Patent number: 9807327
    Abstract: A solid-state imaging device includes: a pixel array section in which a plurality of pixels including an amplification transistor configured to amplify a signal based on a photoelectric charge in accordance with an amount of received light are disposed; through vertical signal lines of the pixel array section, a bias-current control section configured to turn on or off a bias current supplied to the amplification transistor for each of the vertical signal lines; and a drive control section configured to control the bias-current control section so as to turn on the bias current of the vertical signal line through which a pixel signal is read, and to turn off the bias current of the vertical signal line through which a pixel signal is not read.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: October 31, 2017
    Assignee: Sony Corporation
    Inventor: Tomoyasu Tate
  • Publication number: 20170257589
    Abstract: The present disclosure relates to a control device, a control method, and a solid-state imaging device that enable a larger number of shutter row addresses to be set at the same time. A vertical selection decoder and a latch circuit set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses. The present disclosure is applicable to, for example, a CMOS image sensor that sets the shutter row addresses.
    Type: Application
    Filed: August 14, 2015
    Publication date: September 7, 2017
    Inventor: Tomoyasu TATE
  • Publication number: 20160037115
    Abstract: A solid-state imaging device includes: a pixel array section in which a plurality of pixels including an amplification transistor configured to amplify a signal based on a photoelectric charge in accordance with an amount of received light are disposed; through vertical signal lines of the pixel array section, a bias-current control section configured to turn on or off a bias current supplied to the amplification transistor for each of the vertical signal lines; and a drive control section configured to control the bias-current control section so as to turn on the bias current of the vertical signal line through which a pixel signal is read, and to turn off the bias current of the vertical signal line through which a pixel signal is not read.
    Type: Application
    Filed: July 6, 2015
    Publication date: February 4, 2016
    Inventor: Tomoyasu Tate
  • Patent number: 9094627
    Abstract: A solid-state imaging device includes a pixel array section that includes an amplification transistor configured to amplify a signal based on a photoelectric charge in accordance with an amount of received light. Through vertical signal lines of the pixel array section, a bias-current control section is configured to turn on or off a bias current supplied to the amplification transistor for each of the vertical signal lines. A drive control section is configured to control the bias-current control section. In one example, the drive control section controls switching modes between a first mode in which pixel columns whose pixel signals are read are changed in time series, and a second mode in which pixel signals of all the pixel columns are read and then the pixel signals of the plurality of pixel columns are smoothed.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: July 28, 2015
    Assignee: Sony Corporation
    Inventor: Tomoyasu Tate
  • Publication number: 20130306841
    Abstract: A solid-state imaging device includes: a pixel array section in which a plurality of pixels including an amplification transistor configured to amplify a signal based on a photoelectric charge in accordance with an amount of received light are disposed; through vertical signal lines of the pixel array section, a bias-current control section configured to turn on or off a bias current supplied to the amplification transistor for each of the vertical signal lines; and a drive control section configured to control the bias-current control section so as to turn on the bias current of the vertical signal line through which a pixel signal is read, and to turn off the bias current of the vertical signal line through which a pixel signal is not read.
    Type: Application
    Filed: April 11, 2013
    Publication date: November 21, 2013
    Applicant: Sony Corporation
    Inventor: Tomoyasu Tate