Abstract: A data processing device includes: multiple data processing stages including a processing element, a stage memory and an event controller; and a bidirectional slotted bus connecting between the data processing stages, including two write only busses arranged at different data writing directions independently from each other. The processing element and the stage memory in one data processing stage are connected to each other via a read only bus. The processing element and the slotted bus are connected to each other via a write only bus. A process completion event is input from the processing element to the event controller, and an external event is input from an external device to the event controller. The event controller generates a task start event with respect to the processing element, according to each of the process completion event and the external event.

Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Abstract: A data processing device includes: data processing stages having a processing element, a stage memory and an event controller; and an inter-stage bus connecting the stages via an access point. External and process completion events are input into the controller for generating a task start event toward the processing element according to the external and process completion events. Each access point has an access table storing a data write history when the processing element writes data in the memory in a memory access process. The processing element executes an event access process indicative of memory access process completion after the processing element completes the memory access process to the memory via the access point. The access point executes another event access process for inputting the process completion event into the controller of another stage, based on the data write history when the processing element executes the event access process.

Abstract: A task scheduler scheduling running units to execute a plurality of tasks is provided. The task scheduler includes a time control portion having a common time to control a state of the plurality of tasks, and a task calculator calculating a slack disappearance time for each of the plurality of tasks. An arrival time of one of the plurality of tasks is defined as T. A deadline time representing when the one of the plurality of tasks is required to be completed is defined as D. A worst case execution time predicted to be required for a completion of the one of the plurality of tasks is defined as W. A current elapsed time is defined as C. The slack disappearance time is expressed by S=T+D?W+C. A task having an earliest slack disappearance time from among the plurality of tasks is scheduled to be preferentially executed.

Abstract: A data processing device includes: data processing stages having a processing element, a stage memory and an event controller; and an inter-stage bus connecting the stages via an access point. External and process completion events are input into the controller for generating a task start event toward the processing element according to the external and process completion events. Each access point has an access table storing a data write history when the processing element writes data in the memory in a memory access process. The processing element executes an event access process indicative of memory access process completion after the processing element completes the memory access process to the memory via the access point. The access point executes another event access process for inputting the process completion event into the controller of another stage, based on the data write history when the processing element executes the event access process.

Abstract: A data processing device includes: multiple data processing stages including a processing element, a stage memory and an event controller; and a bidirectional slotted bus connecting between the data processing stages, including two write only busses arranged at different data writing directions independently from each other. The processing element and the stage memory in one data processing stage are connected to each other via a read only bus. The processing element and the slotted bus are connected to each other via a write only bus. A process completion event is input from the processing element to the event controller, and an external event is input from an external device to the event controller. The event controller generates a task start event with respect to the processing element, according to each of the process completion event and the external event.

Abstract: A task scheduler scheduling running units to execute a plurality of tasks is provided. The task scheduler includes a time control portion having a common time to control a state of the plurality of tasks, and a task calculator calculating a slack disappearance time for each of the plurality of tasks. An arrival time of one of the plurality of tasks is defined as T. A deadline time representing when the one of the plurality of tasks is required to be completed is defined as D. A worst case execution time predicted to be required for a completion of the one of the plurality of tasks is defined as W. A current elapsed time is defined as C. The slack disappearance time is expressed by S=T+D?W+C. A task having an earliest slack disappearance time from among the plurality of tasks is scheduled to be preferentially executed.

Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.