Patents by Inventor Tomoyoshi Hiei

Tomoyoshi Hiei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352227
    Abstract: An electronic component includes a first insulator layer including thereon a first conductor pattern to define an inductor and a first electrode pattern to define a capacitor, and a second insulator layer including thereon a second conductor pattern to define the inductor and a second electrode pattern to define the capacitor. The first and second electrode patterns face each other across the second insulator layer to define the capacitor, and the second conductor pattern is electrically connected to the first conductor pattern along the first conductor pattern.
    Type: Application
    Filed: July 12, 2023
    Publication date: November 2, 2023
    Inventors: Tomoyoshi HIEI, Kentaro MIKAWA
  • Patent number: 10861757
    Abstract: An electronic component includes a wiring substrate, surface mount devices mounted on a front surface of the wiring substrate, and a shield plate fixed on a side adjacent to top surfaces of the surface mount devices. The shield plate includes a magnetic ceramic sintered sheet and a first metal film. The magnetic ceramic sintered sheet includes a first main surface and a second main surface. The first metal film is disposed on the first main surface of the magnetic ceramic sintered sheet.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirokazu Yazaki, Tomoyoshi Hiei
  • Patent number: 10750609
    Abstract: In a structure for mounting a shielded module on a printed wiring board, the shielded module includes a mounting substrate, a shielding layer, and a solder layer. Electronic components are mounted on a main surface of the mounting substrate. The shielding layer is provided in an area from above the mounting substrate to a side surface of the mounting substrate and covers the electronic components. The solder layer is provided on a side surface of the shielding layer. The shielding layer is connected to a surface electrode located on the printed wiring board via the solder layer. The surface of the solder layer is depressed.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 18, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Norifumi Kobayashi, Tomoyoshi Hiei
  • Publication number: 20190387612
    Abstract: In a structure for mounting a shielded module on a printed wiring board, the shielded module includes a mounting substrate, a shielding layer, and a solder layer. Electronic components are mounted on a main surface of the mounting substrate. The shielding layer is provided in an area from above the mounting substrate to a side surface of the mounting substrate and covers the electronic components. The solder layer is provided on a side surface of the shielding layer. The shielding layer is connected to a surface electrode located on the printed wiring board via the solder layer. The surface of the solder layer is depressed.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Inventors: Norifumi KOBAYASHI, Tomoyoshi HIEI
  • Publication number: 20190363030
    Abstract: An electronic component includes a wiring substrate, surface mount devices mounted on a front surface of the wiring substrate, and a shield plate fixed on a side adjacent to top surfaces of the surface mount devices. The shield plate includes a magnetic ceramic sintered sheet and a first metal film. The magnetic ceramic sintered sheet includes a first main surface and a second main surface. The first metal film is disposed on the first main surface of the magnetic ceramic sintered sheet.
    Type: Application
    Filed: August 13, 2019
    Publication date: November 28, 2019
    Inventors: Hirokazu YAZAKI, Tomoyoshi HIEI
  • Patent number: 9553509
    Abstract: In a multichannel DC-DC converter that reduces radiation noise to a minimum, a wiring line between the coil conductor of a channel having the smallest load current and the switching IC, among the coil conductors defining a plurality of channels, is the longest connection wiring line, such that a channel having the smallest load current is connected to a wiring line that is most likely to radiate noise and radiation noise is reduced to a minimum. A connection wiring line connected to a coil conductor having the largest load current among the plurality of coil conductors is the shortest connection wiring line. A channel having the largest load current is connected to a wiring line that is least likely to radiate noise and, as a result, radiation noise is further reduced.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: January 24, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoyoshi Hiei
  • Patent number: 9320134
    Abstract: A DC-DC converter module includes a multi-layer substrate, a switching IC, and a coil. The multi-layer substrate includes component mounting electrodes provided on the top surface and an input terminal, an output terminal, and ground terminals provided on the bottom surface. The switching IC switches an input voltage and includes an input electrode, an output electrode, and a ground electrode, and is mounted on the top surface of the substrate by connecting the electrodes to the component mounting electrodes. The coil is arranged within the multi-layer substrate in a spiral shape with an axis extending in the substrate stacking direction. The bottom surface side end of the coil is connected to the input/output electrode of the switching IC.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoyoshi Hiei
  • Publication number: 20130229167
    Abstract: In a multichannel DC-DC converter that reduces radiation noise to a minimum, a wiring line between the coil conductor of a channel having the smallest load current and the switching IC, among the coil conductors defining a plurality of channels, is the longest connection wiring line, such that a channel having the smallest load current is connected to a wiring line that is most likely to radiate noise and radiation noise is reduced to a minimum. A connection wiring line connected to a coil conductor having the largest load current among the plurality of coil conductors is the shortest connection wiring line. A channel having the largest load current is connected to a wiring line that is least likely to radiate noise and, as a result, radiation noise is further reduced.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 5, 2013
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Tomoyoshi HIEI
  • Patent number: 7060912
    Abstract: A circuit board comprises a board substrate including a substrate layer formed with a pad on an upper surface thereof, and a metal piece soldered on the pad. At least one through-hole including an internal wall formed with a conductive film is provided at a portion corresponding to the pad on the substrate layer. The through-hole is filled with a predetermined filler for closing at least an open mouth of the through-hole at the upper surface of the substrate layer. The pad is connected integrally with the conductive film on the internal wall of the through-hole.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: June 13, 2006
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsunori Nagashima, Tomoyoshi Hiei
  • Publication number: 20040074669
    Abstract: A circuit board comprises a board substrate including a substrate layer formed with a pad on an upper surface thereof, and a metal piece soldered on the pad. At least one through-hole including an internal wall formed with a conductive film is provided at a portion corresponding to the pad on the substrate layer. The through-hole is filled with a predetermined filler for closing at least an open mouth of the through-hole at the upper surface of the substrate layer. The pad is connected integrally with the conductive film on the internal wall of the through-hole.
    Type: Application
    Filed: December 6, 2002
    Publication date: April 22, 2004
    Inventors: Mitsunori Nagashima, Tomoyoshi Hiei