Patents by Inventor Tomoyuki Arai
Tomoyuki Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969662Abstract: There is provided a robot device including: a head portion coupled to a trunk; four leg portions on a front left, a front right, a rear left, and a rear right coupled to the trunk; a first indirect portion that tilts the head portion left and right; and a second joint portion that rotates, with respect to the trunk, one of the leg portions on the rear left and the rear right to a front side, and the other to a rear side. It is possible to faithfully reproduce the movement of the four-legged animal by providing the first joint portion and the second joint portion.Type: GrantFiled: September 6, 2018Date of Patent: April 30, 2024Assignee: SONY CORPORATIONInventors: Hidenori Ishibashi, Tomoo Mizukami, Takuma Araki, Masato Muraki, Tomoyuki Arai, Goushi Koike, Takayuki Ito, Kouta Katsumura, Yohei Watanabe, Muneyuki Horiguchi, Takashi Maeda, Satoshi Muto, Hideo Miyano
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Publication number: 20240038799Abstract: Provided is a solid-state imaging device capable of acquiring an image with higher image quality. It includes: a substrate; a plurality of photoelectric conversion units in a two-dimensional matrix on the substrate; a lattice-shaped pixel separation unit on the substrate and surrounding the respective photoelectric conversion units; and a lattice-shaped light-shielding film on a side of a light-incident surface of the substrate that includes a plurality of openings that opens the respective plurality of photoelectric conversion units on the light-incident surface side. The light-shielding film has an overhang that overhangs inward of the respective openings at a corner between two mutually intersecting sides of a lattice of the light-shielding film. Each of light-incident surfaces of a plurality of intersections where sides of a lattice of the pixel separation unit intersect one another overlaps with at least one of the lattice of the light-shielding film or the overhang in plan view.Type: ApplicationFiled: June 4, 2021Publication date: February 1, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Tomoyuki ARAI
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Publication number: 20230034691Abstract: A solid-state imaging device according to an embodiment includes: a semiconductor substrate including a photoelectric conversion element; a lens disposed above a first light incident surface of the photoelectric conversion element; and a plurality of columnar structures disposed on a surface parallel to the first light incident surface that is located between a second light incident surface of the lens and the first light incident surface of the photoelectric conversion element. The columnar structure includes at least one of silicon, germanium, gallium phosphide, aluminum oxide, cerium oxide, hafnium oxide, indium oxide, tin oxide, niobium pentoxide, magnesium oxide, tantalum pentoxide, titanium pentoxide, titanium oxide, tungsten oxide, yttrium oxide, zinc oxide, zirconia, cerium fluoride, gadolinium fluoride, lanthanum fluoride, and neodymium fluoride.Type: ApplicationFiled: October 3, 2022Publication date: February 2, 2023Inventors: MIKINORI ITO, YUTA NAKAMOTO, TOMOMI OKANO, YUYA KITABAYASHI, TAKASHI TANAKA, TOMOYUKI ARAI, NATSUKO OOTANI
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Patent number: 11508767Abstract: A solid-state imaging device according to an embodiment includes: a semiconductor substrate including a photoelectric conversion element; a lens disposed above a first light incident surface of the photoelectric conversion element; and a plurality of columnar structures disposed on a surface parallel to the first light incident surface that is located between a second light incident surface of the lens and the first light incident surface of the photoelectric conversion element. The columnar structure includes at least one of silicon, germanium, gallium phosphide, aluminum oxide, cerium oxide, hafnium oxide, indium oxide, tin oxide, niobium pentoxide, magnesium oxide, tantalum pentoxide, titanium pentoxide, titanium oxide, tungsten oxide, yttrium oxide, zinc oxide, zirconia, cerium fluoride, gadolinium fluoride, lanthanum fluoride, and neodymium fluoride.Type: GrantFiled: December 21, 2018Date of Patent: November 22, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Mikinori Ito, Yuta Nakamoto, Tomomi Okano, Yuya Kitabayashi, Takashi Tanaka, Tomoyuki Arai, Natsuko Ootani
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Publication number: 20220173150Abstract: The present technology relates to a solid-state imaging apparatus designed to improve sensitivity while preventing worsening of color mixing. A substrate, a plurality of photoelectric conversion regions provided in the substrate, a color filter provided on the upper side of the photoelectric conversion regions, a trench provided through the substrate and provided between the photoelectric conversion regions, and a recessed region including a plurality of recesses provided on the light-receiving surface side of the substrate above the photoelectric conversion regions are included. The color filter over adjacent two of the photoelectric conversion regions is of the same color. The number of the recesses of the recessed region is larger at a high image height than at an image height center. The present technology can be applied to, for example, a back-illuminated solid-state imaging apparatus etc.Type: ApplicationFiled: March 30, 2020Publication date: June 2, 2022Inventors: TOMOKI KUROSE, TOMOYUKI ARAI, HIROMASA SAITO, SHINJI NAKAGAWA, JUNJI HAYAFUJI, HIROFUMI YAMADA
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Publication number: 20210366964Abstract: A solid-state imaging device according to an embodiment includes: a semiconductor substrate including a photoelectric conversion element; a lens disposed above a first light incident surface of the photoelectric conversion element; and a plurality of columnar structures disposed on a surface parallel to the first light incident surface that is located between a second light incident surface of the lens and the first light incident surface of the photoelectric conversion element. The columnar structure includes at least one of silicon, germanium, gallium phosphide, aluminum oxide, cerium oxide, hafnium oxide, indium oxide, tin oxide, niobium pentoxide, magnesium oxide, tantalum pentoxide, titanium pentoxide, titanium oxide, tungsten oxide, yttrium oxide, zinc oxide, zirconia, cerium fluoride, gadolinium fluoride, lanthanum fluoride, and neodymium fluoride.Type: ApplicationFiled: December 21, 2018Publication date: November 25, 2021Inventors: MIKINORI ITO, YUTA NAKAMOTO, TOMOMI OKANO, YUYA KITABAYASHI, TAKASHI TANAKA, TOMOYUKI ARAI, NATSUKO OOTANI
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Publication number: 20200246982Abstract: There is provided a robot device including: a head portion coupled to a trunk; four leg portions on a front left, a front right, a rear left, and a rear right coupled to the trunk; a first indirect portion that tilts the head portion left and right; and a second joint portion that rotates, with respect to the trunk, one of the leg portions on the rear left and the rear right to a front side, and the other to a rear side. It is possible to faithfully reproduce the movement of the four-legged animal by providing the first joint portion and the second joint portion.Type: ApplicationFiled: September 6, 2018Publication date: August 6, 2020Applicant: SONY CORPORATIONInventors: Hidenori ISHIBASHI, Tomoo MIZUKAMI, Takuma ARAKI, Masato MURAKI, Tomoyuki ARAI, Goushi KOIKE, Takayuki ITO, Kouta KATSUMURA, Yohei WATANABE, Muneyuki HORIGUCHI, Takashi MAEDA, Satoshi MUTO, Hideo MIYANO
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Publication number: 20190093164Abstract: An object of the present invention is to provide a marker for diagnosis of allergic rhinitis, etc. which can accurately diagnose whether allergic rhinitis has developed or not, or the risk of developing allergic rhinitis. It is possible to accurately diagnose whether allergic rhinitis has developed or not, or the risk of developing allergic rhinitis by using human CRLF2 (cytokine receptor-like factor 2) gene or human ETV7 (ETS variant 7) gene or human CRLF2 protein or human ETV7 protein as a biomarker and detecting increased expression of mRNA or cDNA of the gene or increased expression of the protein.Type: ApplicationFiled: February 21, 2017Publication date: March 28, 2019Inventors: Tomoyuki Arai, Yoshitaka Okamato, Daiju Sakurai
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Patent number: 10096640Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.Type: GrantFiled: June 2, 2015Date of Patent: October 9, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Arai, Fumiaki Sano
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Patent number: 9954503Abstract: A differential amplification circuit includes: a first transistor and a second transistor of a differential pair; first and second loads; current sources; and a resistor circuit, wherein the resistor circuit includes: a coarse adjustment part and a fine adjustment part, one of the coarse adjustment part and the fine adjustment part includes a first lateral adjustment part and a second lateral adjustment part which have the same configuration, the first lateral adjustment part and the second lateral adjustment part are connected symmetrically to both sides of a central adjustment part, and the central adjustment part has a circuit configuration symmetrical with respect to two connection nodes with the first lateral adjustment part and the second lateral adjustment part.Type: GrantFiled: February 19, 2015Date of Patent: April 24, 2018Assignee: SOCIONEXT INC.Inventor: Tomoyuki Arai
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Patent number: 9547321Abstract: A temperature sensor circuit includes: an output circuit including a first field-effect transistor configured to output a current proportional to temperature when a voltage twice as high as a threshold voltage is applied to a gate of the first field-effect transistor; and a voltage generating circuit configured to generate the voltage twice as high as the threshold voltage by a plurality of field-effect transistors and supply the generated voltage twice as high as the threshold voltage to the gate of the first field-effect transistor.Type: GrantFiled: November 13, 2015Date of Patent: January 17, 2017Assignee: SOCIONEXT INC.Inventor: Tomoyuki Arai
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Publication number: 20160187901Abstract: A temperature sensor circuit includes: an output circuit including a first field-effect transistor configured to output a current proportional to temperature when a voltage twice as high as a threshold voltage is applied to a gate of the first field-effect transistor; and a voltage generating circuit configured to generate the voltage twice as high as the threshold voltage by a plurality of field-effect transistors and supply the generated voltage twice as high as the threshold voltage to the gate of the first field-effect transistor.Type: ApplicationFiled: November 13, 2015Publication date: June 30, 2016Inventor: Tomoyuki ARAI
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Publication number: 20150325607Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.Type: ApplicationFiled: June 2, 2015Publication date: November 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Tomoyuki ARAI, Fumiaki SANO
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Publication number: 20150280666Abstract: A differential amplification circuit includes: a first transistor and a second transistor of a differential pair; first and second loads; current sources; and a resistor circuit, wherein the resistor circuit includes: a coarse adjustment part and a fine adjustment part, one of the coarse adjustment part and the fine adjustment part includes a first lateral adjustment part and a second lateral adjustment part which have the same configuration, the first lateral adjustment part and the second lateral adjustment part are connected symmetrically to both sides of a central adjustment part, and the central adjustment part has a circuit configuration symmetrical with respect to two connection nodes with the first lateral adjustment part and the second lateral adjustment part.Type: ApplicationFiled: February 19, 2015Publication date: October 1, 2015Inventor: Tomoyuki ARAI
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Patent number: 9076705Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.Type: GrantFiled: March 15, 2012Date of Patent: July 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Arai, Fumiaki Sano
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Patent number: 9008231Abstract: A method may include receiving a positive in-phase (“I”)-channel signal (“I+ signal”), a negative I-channel signal (“I? signal”), a positive quadrature-phase (“Q”)-channel signal (“Q+ signal”), and a negative Q-channel signal (“Q? signal”). The method may further include outputting a truncated I+ signal, a truncated I? signal, a truncated Q+ signal, and a truncated Q? signal. The method may further include generating the truncated I+ signal based on the I+ and Q+ signals and a complement of the truncated Q? signal, generating the truncated I? signal based on the I? and Q? signals and a complement of the truncated Q+ signal, generating the truncated Q+ signal based on the I? and Q+ signals and a complement of the truncated I+ signal, and generating the truncated Q? signal based on the I+ and Q? signals and a complement of the truncated I? signal.Type: GrantFiled: May 31, 2013Date of Patent: April 14, 2015Assignee: Intel IP CorporationInventors: Tomoyuki Arai, Patrick Rakers
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Publication number: 20140355701Abstract: A method may include receiving a positive in-phase (“I”)-channel signal (“I+ signal”), a negative I-channel signal (“I? signal”), a positive quadrature-phase (“Q”)-channel signal (“Q+ signal”), and a negative Q-channel signal (“Q? signal”). The method may further include outputting a truncated I+ signal, a truncated I? signal, a truncated Q+ signal, and a truncated Q? signal. The method may further include generating the truncated I+ signal based on the I+ and Q+ signals and a complement of the truncated Q? signal, generating the truncated I? signal based on the I? and Q? signals and a complement of the truncated Q+ signal, generating the truncated Q+ signal based on the I? and Q+ signals and a complement of the truncated I+ signal, and generating the truncated Q? signal based on the I+ and Q? signals and a complement of the truncated I? signal.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Applicant: Intel IP CorporationInventors: Tomoyuki ARAI, Patrick RAKERS
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Publication number: 20130043550Abstract: Certain embodiments provide a solid-state imaging apparatus including a first impurity layer, a second impurity layer, a third impurity layer, and an electrode. The first impurity layer is a photoelectric conversion layer, and is formed to have a constant depth on a semiconductor substrate. The second impurity layer is formed on a surface of the first impurity layer, to have a depth which becomes shallower toward a direction from the first impurity layer to the third impurity layer. The third impurity layer is formed in a position spaced apart from the first impurity layer and the second impurity layer on the surface of the semiconductor substrate. The electrode can transport electric charges from the first impurity layer to the third impurity layer, and is formed between the second impurity layer and the third impurity layer, on the surface of the semiconductor substrate.Type: ApplicationFiled: March 15, 2012Publication date: February 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tomoyuki ARAI, Fumiaki SANO
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Patent number: 8283980Abstract: An amplifier circuit includes an amplifier unit and a current control circuit as means for achieving the aforementioned object. The amplifier unit includes a gain compensation MOS transistor compensating for gain of an output characteristic and a linearity compensation MOS transistor compensating for linearity of an output characteristic. A source of the gain compensation MOS transistor is connected to a drain of the linearity compensation MOS transistor. An input signal is applied to a gate of the linearity compensation MOS transistor. A drain of the gain compensation MOS transistor is set as an output. The current control circuit performs control so as to pass predetermined current between the drain and the source of the gain compensation MOS transistor and pass predetermined current between the drain and the source of the linearity compensation MOS transistor.Type: GrantFiled: September 25, 2009Date of Patent: October 9, 2012Assignee: Fujitsu LimitedInventors: Tomoyuki Arai, Masahiro Kudo, Shinji Yamaura
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Patent number: 7928803Abstract: An amplifying circuit includes amplifying unit comprising a first transistor unit having a gate width that is controllable and is controlled based on a first control signal.Type: GrantFiled: January 6, 2010Date of Patent: April 19, 2011Assignee: Fujitsu LimitedInventor: Tomoyuki Arai