Patents by Inventor Tomoyuki Asada
Tomoyuki Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7145397Abstract: Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.Type: GrantFiled: July 13, 2004Date of Patent: December 5, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuya Yamamoto, Teruyuki Shimura, Tomoyuki Asada, Satoshi Suzuki
-
Publication number: 20050030106Abstract: Disclosed is an output overvoltage protection circuit for a power amplifier having a plurality of stages, which comprises a monitor circuit for monitoring an output overvoltage of an output transistor in the final stage of the power amplifier and allowing a current to flow therethrough in response to the monitored output overvoltage, and a current mirror circuit for supplying a current proportional to the current from the monitor circuit in such a manner that the base bias of the first-stage transistor of the power amplifier is reduced in response to the current supplied from the current mirror circuit, to reduce the output of the final-stage output transistor.Type: ApplicationFiled: July 13, 2004Publication date: February 10, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazuya Yamamoto, Teruyuki Shimura, Tomoyuki Asada, Satoshi Suzuki
-
Publication number: 20030218500Abstract: An amplification part of a power amplifier includes first to third amplifier stages and a signal transmission part provided in parallel with the first amplifier stage. When a mode select voltage Vmod2 is set to the L level, an input signal is amplified by the first to third amplifier stages. At this time, the signal transmission part does not transmit signals. On the other hand, when mode select voltage Vmod2 is set to the H level, the signal transmission part transmits the input signal to a transistor via a diode. At this time, a control voltage Vmod1800 is set to the L level, and the first amplifier stage is turned off, so that power consumption is reduced. Thus, a power amplifier capable of switching a gain in accordance with GSM/EDGE modes while suppressing noise power in a reception band can be provided.Type: ApplicationFiled: November 19, 2002Publication date: November 27, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazuya Yamamoto, Teruyuki Shimura, Tomoyuki Asada, Satoshi Suzuki
-
Patent number: 6570451Abstract: A high-frequency power amplifier includes a semi-insulating GaAs substrate having disposed thereon an amplifying bipolar transistor, a bias circuit, a bias circuit output terminal connected to the bias circuit, and a base electrode connection terminal connected to the bipolar transistor; a chip inductor connected between the bias circuit output terminal and the base electrode connection terminal; and a mounting substrate on which both the semi-insulating GaAs substrate and the chip inductor are disposed, side by side.Type: GrantFiled: May 7, 2001Date of Patent: May 27, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tomoyuki Asada
-
Publication number: 20020063602Abstract: The present invention provides a high-frequency power amplifier comprising: a semi-insulating GaAs substrate 18 having disposed thereon an amplifier bipolar transistor 20, a bias circuit 26, a bias circuit output terminal 32 connected to the bias circuit 26, and a base electrode connection terminal 34 connected to the bipolar transistor 20; a chip inductor 16 connected between the bias circuit output terminal 32 and the base electrode connection terminal 34; and a mounting substrate 12 on which both the semi-insulating GaAs substrate 18 and the chip inductor 16 are disposed, side by side.Type: ApplicationFiled: May 7, 2001Publication date: May 30, 2002Inventor: Tomoyuki Asada
-
Patent number: 6278328Abstract: While minimizing any increase in chip size and without incurring a loss in performance or operating characteristic under normal operating voltage conditions, a power amplifier protection circuit effectively prevents breakdown of power amplifying transistors resulting from output load fluctuations during operation with an overvoltage supply. The protection circuit includes a gate circuit electrically connected between the collector and base of at least the last-stage transistor in a power amplifier including transistors connected in stages. The gate circuit passes a feedback current to the base electrode of the protected transistor when a voltage exceeding a specific level is applied to the collector of the protected transistor.Type: GrantFiled: November 19, 1999Date of Patent: August 21, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuya Yamamoto, Akira Inoue, Satoshi Suzuki, Tomoyuki Asada
-
Patent number: 6240262Abstract: A toner supply device comprises: a toner cartridge, which is used for an image forming system, including a substantially cylindrical container for housing therein a toner and which is supplied when the toner is insufficient for the image forming system; an information recording part which is provided on the peripheral surface of the container and on which information including that the toner is a certified product has been recorded; a rotating unit, connected to the tip portion of the container when the container is attached, for rotating the container along the peripheral surface; a cleaning unit, provided in the vicinity of the container, for contacting the information recording part of the container in response to the operation of the rotating unit during the reading operation of a reading sensor, to sequentially clean the information recording part by the rotation of the container; and a reading sensor, provided in the vicinity of the container and in front of the cleaning unit in rotational directions ofType: GrantFiled: February 18, 2000Date of Patent: May 29, 2001Assignee: Toshiba Tec Kabushiki KaishaInventors: Yoshiharu Taniyama, Tomoyuki Asada, Shinichi Itoh
-
Patent number: 5016560Abstract: A developing device for developing an electrostatic latent image formed on an image carrier includes a roller which carries toner particles to the developing position and a porous foam member of a material such as urethane resin which contacts the roller. The porous foam member comes in contact with either a developing roller or a toner supply roller which supplies toner particles to the developing roller. Toner particles supported in the holes of the porous foam member are charged as the particles rub against the developing roller or toner supply roller, causing the particles to be readily transferred to the roller. The porous foam member causes the amount of toner particles supported on the surface of the developing roller or the toner-supply roller to be sufficient to prevent a reduction in the density of the toner image even directly after a larger amount of toner particles are consumed for developing a solid toner region for example.Type: GrantFiled: April 25, 1989Date of Patent: May 21, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Asada, Kaoru Nishida, Mamoru Shimono, Hideyuki Shinohara, Koichi Ando
-
Patent number: 5012283Abstract: A copying apparatus includes a housing in which are arranged an image carrier and an exposure unit both for emitting light to an original placed on the original stand to form an electrostatic latent image on the image carrier and for emitting light to the image carrier to erase the electrostatic latent image. The exposure unit includes a lamp having light emitting portions and non-light emitting portions which are alternately connected together. A reflector is located around the lamp and directs the light emitted from the lamp toward the original. The reflector has a plurality of openings formed to face the lamp, so that part of the light emitted from the lamp passes through the openings and is directed to the image carrier. The reflector has a plurality of connecting portions facing the non-light-emitting portions and located between adjacent ones of the openings.Type: GrantFiled: January 17, 1990Date of Patent: April 30, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Mamoru Shimono, Tomoyuki Asada, Taiichi Kawaguchi, Yoichi Taya, Kouji Yukinaga, Susumu Nomura, Hajime Tagawa
-
Patent number: 4806992Abstract: In a developing apparatus for developing an electrostatic-latent image by applying a charged developer to the electrostatic-latent image formed on a surface of an image carrier, a housing which stores the developer has a developing roller for feeding the developer therefrom to a developing position. A developer supply roller for supplying a triboelectrically charged developer is in rolling contact with the developer roller. The developer supply roller has a conductive material, and is rotated while electrostatically holding a developer so as to charge it by friction.Type: GrantFiled: February 24, 1987Date of Patent: February 21, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Sachiko Yasuda, Minoru Yoshida, Tomoyuki Asada, Hideo Mukai
-
Patent number: 4780743Abstract: A device for transferring charged developing particles onto an electrostatic latent image, comprising a reservoir for holding a quantity of developing particles, a multilayered developing roller rotatably exposed to the quantity of developing particles, including a surface layer for frictionally charging the developing particles with a specified polarity and for attracting the charged developing particles for forming a coating of charged developing particles on the surface layer, and an image carrier for supporting the electrostatic latent image in proximity to the developing roller, the latent image having a polarity opposite to the specified polarity for attracting the charged developing particles from the coating onto the latent image.Type: GrantFiled: March 30, 1987Date of Patent: October 25, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Asada, Kiyoshi Tomimori
-
Patent number: 4748472Abstract: In a developing apparatus for developing an electrostatic latent image by applying a charged developer to the latent image formed on the surface of an image carrier, a housing, stored with the developer, is provided with a developing roller for feeding the developer therefrom to a developing position. A plurality of blades are pressed against the developing roller, whereby the developer is triboelectrically charged.Type: GrantFiled: February 13, 1987Date of Patent: May 31, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Mukai, Tomoyuki Asada