Patents by Inventor TOMOYUKI ASHIMINE
TOMOYUKI ASHIMINE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830909Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; and a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer. Moreover, the protective layer is provided to expose an outer peripheral end on the first main surface of the semiconductor substrate. The semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer.Type: GrantFiled: February 22, 2022Date of Patent: November 28, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tomoyuki Ashimine, Yuji Irie, Yasuhiro Murase
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Patent number: 11605503Abstract: A capacitor that includes an insulating base material having a first main surface and a second main surface facing each other, the insulating base material defining first and second trenches extending from the first main surface into the base material such that first trench and the second trench overlap each other; a first conductor in the first trench; a first external electrode on the first main surface of the base material and connected to the first conductor; a second conductor in the second trench; and a second external electrode on the second main surface of the base material and connected to the second conductor.Type: GrantFiled: February 4, 2020Date of Patent: March 14, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Patent number: 11488784Abstract: A capacitor that includes a substrate having a main surface with at least one of a recess or a projection, a dielectric film extending along the at least one of the recess or the projection and having an equivalent oxide thickness of 600 nm or more, and a conductor film covering at least part of the dielectric film.Type: GrantFiled: August 20, 2020Date of Patent: November 1, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Patent number: 11476056Abstract: A capacitor that includes a substrate, a dielectric portion, and a conductor layer. The dielectric portion includes a thick film portion and a thin film portion. The thick film portion has a thickness larger than the average thickness of the dielectric portion in a direction perpendicular to the first main surface. The thin film portion has a thickness smaller than the average thickness of the dielectric portion in the direction perpendicular to the first main surface. The thick film portion has a larger relative permittivity than the thin film portion.Type: GrantFiled: October 8, 2020Date of Patent: October 18, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hiroshi Nakagawa, Tomoyuki Ashimine, Yasuhiro Murase
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Publication number: 20220181436Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; and a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer. Moreover, the protective layer is provided to expose an outer peripheral end on the first main surface of the semiconductor substrate. The semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Inventors: Tomoyuki ASHIMINE, Yuji IRIE, Yasuhiro MURASE
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Publication number: 20220139795Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface; a dielectric film on the first main surface, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in a first outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion; a first electrode layer on the electrode layer disposing portion; a first protective layer covering a second outer peripheral end of the first electrode layer and at least a part of the protective layer covering portion; and a second protective layer covering the first protective layer, wherein the first protective layer has a relative permittivity lower than that of the second protective layer, and the second protective layer has moisture resistance higher than that of the first protective layer.Type: ApplicationFiled: January 21, 2022Publication date: May 5, 2022Inventors: Yohei YAMAGUCHI, Tomoyuki ASHIMINE, Yasuhiro MURASE
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Publication number: 20220115336Abstract: A semiconductor device that includes a semiconductor substrate having a first main face and a second main face opposite each other; a dielectric film on a part of the first main face, the dielectric film having an electrode layer disposing portion and a protective layer covering portion, and a thickness of the protective layer covering portion in an outer peripheral end of the dielectric film is smaller than a thickness of the electrode layer disposing portion of the dielectric film; a first electrode layer on the electrode layer disposing portion of the dielectric film; and a protective layer continuously covering a range from an end portion of the first electrode layer to the outer peripheral end of the dielectric film.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Yohei Yamaguchi, Tomoyuki Ashimine
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Patent number: 11303201Abstract: A CR snubber element includes a first resistance part, a first capacitance part, a second resistance part, and a second capacitance part. The first capacitance part is connected in series to the first resistance part. The second resistance part is connected in series to the first resistance part and the first capacitance part and the second capacitance part is connected in parallel to the second resistance part. The CR snubber element is configured such that the second resistance part is disconnected when the first capacitance part is short-circuited.Type: GrantFiled: September 17, 2020Date of Patent: April 12, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Patent number: 11239226Abstract: A semiconductor apparatus that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a second electrode opposing the second main surface of the semiconductor substrate, and a resistance control layer between the semiconductor substrate and the second electrode. The resistance control layer includes a first region having a first electrical resistivity and electrically connecting the semiconductor substrate and the second electrode, and a second region having a second electrical resistivity higher than the first electrical resistivity of the first region and adjacent to the first region.Type: GrantFiled: May 26, 2020Date of Patent: February 1, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Patent number: 11239159Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a first resistance control layer on the first electrode, a wiring part on the first resistance control layer, and a second electrode opposing the second main surface of the semiconductor substrate. The first resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the first electrode and the wiring part, and a second region that is aligned with the first region and has a second electrical resistivity higher than the first electrical resistivity of the first region.Type: GrantFiled: May 14, 2020Date of Patent: February 1, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Patent number: 11145711Abstract: A capacitor that includes a substrate having a principal surface; a dielectric film on the principal surface of the substrate; and an electrode layer on the dielectric film. The substrate has a recess structure portion with at least one recess portion in a second region outside a first region where the electrode layer overlaps the dielectric layer when viewed in a plan view from a normal direction of the principal surface of the substrate, and the dielectric film is on the recess structure portion.Type: GrantFiled: August 21, 2019Date of Patent: October 12, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Patent number: 10991509Abstract: A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.Type: GrantFiled: October 30, 2019Date of Patent: April 27, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hiroshi Nakagawa, Tomoyuki Ashimine, Yasuhiro Murase
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Publication number: 20210027950Abstract: A capacitor that includes a substrate, a dielectric portion, and a conductor layer. The dielectric portion includes a thick film portion and a thin film portion. The thick film portion has a thickness larger than the average thickness of the dielectric portion in a direction perpendicular to the first main surface. The thin film portion has a thickness smaller than the average thickness of the dielectric portion in the direction perpendicular to the first main surface. The thick film portion has a larger relative permittivity than the thin film portion.Type: ApplicationFiled: October 8, 2020Publication date: January 28, 2021Inventors: Hiroshi Nakagawa, Tomoyuki Ashimine, Yasuhiro Murase
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Patent number: 10903309Abstract: A capacitor that includes a substrate having a first main surface and a second main surface that are opposite to each other, and a plurality of trench portions on the first main surface; a dielectric film adjacent the first main surface of the substrate and extending into interiors of the plurality of trench portions; a conductor film on the dielectric film and extending into the interiors of the plurality of trench portions; and a bonding pad electrically connected to the conductor film. In a plan view from a direction normal to the first main surface of the substrate, the plurality of trench portions are arranged in second regions disposed along a second direction and not in first regions disposed along a first direction in which a bonding wire electrically connected to the bonding pad extends.Type: GrantFiled: December 10, 2019Date of Patent: January 26, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masaki Takeuchi, Tomoyuki Ashimine
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Publication number: 20210006151Abstract: A CR snubber element includes a first resistance part, a first capacitance part, a second resistance part, and a second capacitance part. The first capacitance part is connected in series to the first resistance part. The second resistance part is connected in series to the first resistance part and the first capacitance part and the second capacitance part is connected in parallel to the second resistance part. The CR snubber element is configured such that the second resistance part is disconnected when the first capacitance part is short-circuited.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Patent number: 10879347Abstract: A capacitor that includes a first capacitor layer having a first substrate provided with a first trench structure having a trench, a first electrode, and a second electrode provided in a region of the first trench structure that includes a trench, and a second capacitor layer having a second substrate, a third electrode, and a fourth electrode. Moreover, the first capacitor layer and the second capacitor layer are disposed such that the second electrode and the third electrode oppose each other and are electrically connected.Type: GrantFiled: July 25, 2019Date of Patent: December 29, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Publication number: 20200381181Abstract: A capacitor that includes a substrate having a main surface with at least one of a recess or a projection, a dielectric film extending along the at least one of the recess or the projection and having an equivalent oxide thickness of 600 nm or more, and a conductor film covering at least part of the dielectric film.Type: ApplicationFiled: August 20, 2020Publication date: December 3, 2020Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Publication number: 20200286880Abstract: A semiconductor apparatus that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a second electrode opposing the second main surface of the semiconductor substrate, and a resistance control layer between the semiconductor substrate and the second electrode. The resistance control layer includes a first region having a first electrical resistivity and electrically connecting the semiconductor substrate and the second electrode, and a second region having a second electrical resistivity higher than the first electrical resistivity of the first region and adjacent to the first region.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase
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Publication number: 20200273796Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a first resistance control layer on the first electrode, a wiring part on the first resistance control layer, and a second electrode opposing the second main surface of the semiconductor substrate. The first resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the first electrode and the wiring part, and a second region that is aligned with the first region and has a second electrical resistivity higher than the first electrical resistivity of the first region.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Yasuhiro Murase, Tomoyuki Ashimine, Hiroshi Nakagawa
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Publication number: 20200176614Abstract: A capacitor that includes an insulating base material having a first main surface and a second main surface facing each other, the insulating base material defining first and second trenches extending from the first main surface into the base material such that first trench and the second trench overlap each other; a first conductor in the first trench; a first external electrode on the first main surface of the base material and connected to the first conductor; a second conductor in the second trench; and a second external electrode on the second main surface of the base material and connected to the second conductor.Type: ApplicationFiled: February 4, 2020Publication date: June 4, 2020Inventors: Tomoyuki Ashimine, Hiroshi Nakagawa, Yasuhiro Murase