Patents by Inventor Tomoyuki Hamano
Tomoyuki Hamano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9406395Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell and a controller. The controller controls a write operation. The write operation includes a first program to write data into the first memory cell, and a first verification to verify the first program. when a power voltage has become lower than a first voltage during the execution of the first verification for the first memory cell, the controller executes a second verification to verify the first program for the first memory cell.Type: GrantFiled: September 3, 2015Date of Patent: August 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takuyo Kodama, Masahiro Hosoya, Tomoyuki Hamano
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Patent number: 9171631Abstract: According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.Type: GrantFiled: March 15, 2013Date of Patent: October 27, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko Kamata, Yuko Yokota, Koji Tabata, Tomoyuki Hamano, Mario Sako
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Patent number: 9042183Abstract: According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.Type: GrantFiled: September 6, 2013Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiko Kamata, Koji Tabata, Tomoyuki Hamano
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Publication number: 20140286104Abstract: According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit.Type: ApplicationFiled: September 6, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko KAMATA, Koji TABATA, Tomoyuki HAMANO
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Publication number: 20130279254Abstract: According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch.Type: ApplicationFiled: March 15, 2013Publication date: October 24, 2013Inventors: Yoshihiko KAMATA, Koji TABATA, Mitsuhiro KOGA, Tomoyuki HAMANO, Yuko YOKOTA
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Publication number: 20130279255Abstract: According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.Type: ApplicationFiled: March 15, 2013Publication date: October 24, 2013Inventors: Yoshihiko KAMATA, Yuko YOKOTA, Koji TABATA, Tomoyuki HAMANO, Mario SAKO
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Patent number: 8259523Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.Type: GrantFiled: July 15, 2010Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshifumi Watanabe, Tomoyuki Hamano, Shigefumi Ishiguro, Kazuto Uehara
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Patent number: 8223569Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.Type: GrantFiled: July 15, 2010Date of Patent: July 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Hamano, Shigefumi Ishiguro, Toshifumi Watanabe, Kazuto Uehara
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Publication number: 20110013452Abstract: According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.Type: ApplicationFiled: July 15, 2010Publication date: January 20, 2011Inventors: Toshifumi WATANABE, Tomoyuki HAMANO, Shigefumi ISHIGURO, Kazuto UEHARA
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Publication number: 20110013472Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.Type: ApplicationFiled: July 15, 2010Publication date: January 20, 2011Inventors: Tomoyuki HAMANO, Shigefumi Ishiguro, Toshifumi Watanabe, Kazuto Uehara
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Patent number: 7606083Abstract: A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.Type: GrantFiled: October 1, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Hamano, Shigefumi Ishiguro
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Publication number: 20080253198Abstract: A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.Type: ApplicationFiled: October 1, 2007Publication date: October 16, 2008Inventors: Tomoyuki Hamano, Shigefumi Ishiguro
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Patent number: 5337286Abstract: A semiconductor memory device is adapted for storing, as a unit of memory information, multiple-bit data constituted by signal data comprised of bit data of 2.sup.n bits (n is a natural number) and remainder data comprised of bit data of C bits (C is a natural number, C<2.sup.n). This semiconductor memory device includes a plurality of circuit blocks comprising, e.g., two memory cell groups each comprised of a plurality of memory cells, and a row decoder and a column decoder adapted for allowing respective desired ones of the memory cells within the memory cell groups to be selectively active. Thus, the row decoder and the column decoder become operative so that the bit data serving as the signal data is assigned to one or plural circuit blocks by one bit or plural bits, and the bit data serving as the remainder data is assigned to any circuit block in which bit assignment has been made.Type: GrantFiled: December 21, 1992Date of Patent: August 9, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Ohto, Tomoyuki Hamano, Eiji Kozuka, Naokazu Miyawaki