Patents by Inventor Tomoyuki Isomura

Tomoyuki Isomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8079010
    Abstract: A wiring information generating apparatus includes an input unit that inputs a wiring layer number indicating a wiring layer, a via layer number indicating a next via layer to connect the wiring layer, and spacing information based on wiring rules. A storage unit stores a terminal figure table providing terminal figures, a logic element device wire protected area table, and a wire protected area table. A wire protected area creation unit adds an area of a terminal figure and a logic element device wire protected area obtained by searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number and acquires wire layer-via layer spacing information. A wiring information generating unit generates wiring information in the wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and wire protected area information.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Limited
    Inventor: Tomoyuki Isomura
  • Publication number: 20100077373
    Abstract: A wiring information generating apparatus includes an input unit that inputs a wiring layer number indicating a wiring layer, a via layer number indicating a next via layer to connect the wiring layer, and spacing information based on wiring rules. A storage unit stores a terminal figure table providing terminal figures, a logic element device wire protected area table, and a wire protected area table. A wire protected area creation unit adds an area of a terminal figure and a logic element device wire protected area obtained by searching the terminal figure table and the logic element device wire protected area table based on the input wiring layer number and/or via layer number and acquires wire layer-via layer spacing information. A wiring information generating unit generates wiring information in the wiring layer based on connection information and arrangement information of the semiconductor logic circuit, and wire protected area information.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 25, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Tomoyuki ISOMURA
  • Patent number: 7240317
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: July 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Patent number: 7240318
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: July 3, 2007
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Publication number: 20040153988
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.
    Type: Application
    Filed: July 24, 2003
    Publication date: August 5, 2004
    Applicant: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Publication number: 20040148582
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.
    Type: Application
    Filed: July 24, 2003
    Publication date: July 29, 2004
    Applicant: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Patent number: 6629305
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out Thereby and afterwards executes the program.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: September 30, 2003
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Publication number: 20020042904
    Abstract: The present invention provides a placement/net wiring processing system using an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring.
    Type: Application
    Filed: March 20, 2001
    Publication date: April 11, 2002
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Patent number: 6240541
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: May 29, 2001
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi
  • Patent number: 6223328
    Abstract: The invention concerns a technique of a wiring processing method used in designing, for example, a large scale integrated circuit.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: April 24, 2001
    Assignee: Fujitsu, Limited
    Inventors: Noriyuki Ito, Tomoyuki Isomura, Hiroshi Ikeda, Toshihiko Tada
  • Patent number: 5889677
    Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: March 30, 1999
    Assignee: Fujitsu Limited
    Inventors: Mitsuru Yasuda, Hiroyuki Sugiyama, Noriyuki Ito, Ryoichi Yamashita, Tadashi Konno, Yasunori Abe, Naomi Bizen, Terunobu Maruyama, Yoshiyuki Kato, Tomoyuki Isomura, Hiroshi Ikeda, Miki Takagi