Patents by Inventor Tomoyuki Ito

Tomoyuki Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12713657
    Abstract: The present invention addresses the problem of: realizing a TFT that uses an oxide semiconductor and that is capable of maintaining stable characteristics even in the case where the TFT is miniaturized; and realizing a display device that has high-definition pixels using such a TFT. To solve this problem, the present invention has the following configuration. A semiconductor device including an oxide semiconductor TFT formed using an oxide semiconductor film 109, the semiconductor device being characterized in that: the channel length of the oxide semiconductor TFT is 1.3 to 2.3 ?m; and the sheet resistance of a source region 1092 and a drain region 1091 of the oxide semiconductor film 109 is 1.4 to 20 K?/?.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: August 18, 2026
    Assignee: MAGNOLIA WHITE CORPORATION
    Inventors: Isao Suzumura, Hajime Watakabe, Akihiro Hanada, Ryo Onodera, Tomoyuki Ito
  • Publication number: 20260204353
    Abstract: A method may produce an antibody through machine learning. Such a method of producing an antibody may be optimized for a plurality of characteristics including at least two of an expression level, binding activity, stability, and solubility; and the like. Such a method may include: (1) providing a library comprising mutants prepared by modifying at least some of residues not being an amino acid of the highest appearance frequency in a group of antibody sequences of a target antibody into the amino acid of the highest appearance frequency; (2) determining respective characteristic values indicating the plurality of characteristics of some mutants in the library, and scoring the characteristic values as one value per mutant by normalizing and integrating the characteristic values; (3) conducting machine learning using the score values and ranking the mutants; and (4) selecting an antibody optimized for the plurality of characteristics based on ranking results.
    Type: Application
    Filed: December 1, 2023
    Publication date: July 16, 2026
    Applicants: RevolKa Ltd., TOHOKU UNIVERSITY
    Inventors: Naoyuki KUWABARA, Emi SUZUKI, Taishi KONDO, Yuki TAMURA, Hikaru NAKAZAWA, Ryo YAMAZAKI, Tomoyuki ITO, Misaki TAKAHASHI, Sakiya KAWADA, Mitsuo UMETSU, Shiro KATAOKA
  • Publication number: 20250182853
    Abstract: A method for producing a nucleic acid library. The method includes: preparing, by a phage display method, a first library composed of mutants obtained by randomly introducing a mutation into a nucleic acid sequence encoding a protein bound to or configured to be bound to a target; performing biopanning on the first library and obtaining data to be used for machine learning from an obtained sublibrary; and performing machine learning using the data and obtaining a second library from the first library based on machine learning prediction. The data to be used for machine learning includes a sequence of a mutant population included in a sublibrary at a target-binding sequence elution stage, an estimated binding strength to the target, and an actual measurement value of binding of some mutants included in the mutant population to the target.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 5, 2025
    Applicants: TOHOKU UNIVERSITY, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Mitsuo UMETSU, Hikaru NAKAZAWA, Tomoyuki ITO, Sakiya KAWADA, Hafumi NISHI, Tomoshi KAMEDA, Yutaka SAITO, Thuy Duong NGUYEN, Yoichi KURUMIDA, Koji TSUDA
  • Publication number: 20250104809
    Abstract: The present invention relates to a method of producing a protein for which two or more characteristics are optimized simultaneously. More specifically, the present invention relates to a method of producing a protein for which two or more characteristics are optimized, the method comprising: 1) providing a library comprising mutants from random mutation of a target protein; 2) determining respective characteristic values that indicate the two or more characteristics of some of the mutants in the library, and scoring the two or more characteristic values as one value per mutant by normalizing and integrating the characteristic values; 3) conducting machine learning by using the score values and ranking the library; and 4) selecting a protein for which two or more characteristics are optimized, based on the ranking results, wherein the two or more characteristic values are numerical values based on different measurement data related to respective different characteristics.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 27, 2025
    Applicants: REVOLKA LTD., TOHOKU UNIVERSITY
    Inventors: Hikaru NAKAZAWA, Tomoyuki ITO, Daichi KURIHARA, Sakiya KAWADA, Mitsuo UMETSU, Shiro KATAOKA, Ryo YAMAZAKI
  • Patent number: 12166131
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 10, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Tomoyuki Ito, Toshihide Jinnai, Isao Suzumura, Akihiro Hanada, Ryo Onodera
  • Patent number: 12158661
    Abstract: A display device includes a first nitride insulating film arranged on a first substrate, a gate electrode arranged along a first direction on the first nitride insulating film, a second nitride insulating film arranged on the gate electrode, a first oxide insulating film arranged on the second nitride insulating film, and an oxide semiconductor layer arranged on the first oxide insulating film, wherein the gate electrode has a first titanium layer, an aluminum layer, and a second titanium layer stacked in order from the first nitride insulating film side, and a thickness of the second titanium layer is greater than a thickness of the first titanium layer.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: December 3, 2024
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Takuo Kaitoh, Ryo Onodera, Tomoyuki Ito, Yoshinori Tanaka
  • Patent number: 12105388
    Abstract: A display device includes a wiring region including a gate wiring, a source wiring intersecting the gate wiring, and a first insulating layer between the gate wiring and the source wiring and an opening region including a pixel electrode on the first insulating layer and adjacent to the wiring region. The first insulating layer includes a first oxide insulating layer and a first nitride insulating layer, the first oxide insulating layer is disposed over the wiring region and the opening region, the first nitride insulating layer is disposed in the wiring region and includes a first opening overlapping the opening region, and the pixel electrode overlaps the first opening.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: October 1, 2024
    Assignee: Japan Display Inc.
    Inventors: Akihiro Hanada, Takuo Kaitoh, Tomoyuki Ito, Yoshinori Tanaka
  • Patent number: 12068399
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device, includes forming a first insulating film which covers a gate electrode, forming an island-shaped oxide semiconductor in contact with the first insulating film, forming a second insulating film which covers the oxide semiconductor, forming a source electrode in contact with the oxide semiconductor, forming a drain electrode in contact with the oxide semiconductor, forming a third insulating film which covers the source electrode and the drain electrode and forming a channel region between the source electrode and the drain electrode by supplying oxygen from the third insulating film to the oxide semiconductor via the second insulating film.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: August 20, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Akihiro Hanada, Takuo Kaitoh, Ryo Onodera, Takashi Okada, Tomoyuki Ito, Toshiki Kaneko
  • Publication number: 20240168335
    Abstract: A display device includes a first nitride insulating film arranged on a first substrate, a gate electrode arranged along a first direction on the first nitride insulating film, a second nitride insulating film arranged on the gate electrode, a first oxide insulating film arranged on the second nitride insulating film, and an oxide semiconductor layer arranged on the first oxide insulating film, wherein the gate electrode has a first titanium layer, an aluminum layer, and a second titanium layer stacked in order from the first nitride insulating film side, and a thickness of the second titanium layer is greater than a thickness of the first titanium layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 23, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Takuo KAITOH, Ryo ONODERA, Tomoyuki ITO, Yoshinori TANAKA
  • Publication number: 20240160069
    Abstract: A display device includes a wiring region including a gate wiring, a source wiring intersecting the gate wiring, and a first insulating layer between the gate wiring and the source wiring and an opening region including a pixel electrode on the first insulating layer and adjacent to the wiring region. The first insulating layer includes a first oxide insulating layer and a first nitride insulating layer, the first oxide insulating layer is disposed over the wiring region and the opening region, the first nitride insulating layer is disposed in the wiring region and includes a first opening overlapping the opening region, and the pixel electrode overlaps the first opening.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Applicant: Japan Display Inc.
    Inventors: Akihiro HANADA, Takuo KAITOH, Tomoyuki ITO, Yoshinori TANAKA
  • Publication number: 20230317853
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Application
    Filed: June 5, 2023
    Publication date: October 5, 2023
    Applicant: Japan Display Inc.
    Inventors: Hajime WATAKABE, Tomoyuki ITO, Toshihide JINNAI, lsao SUZUMURA, Akihiro HANADA, Ryo ONODERA
  • Publication number: 20230268572
    Abstract: A power storage device includes power storage cells that are stacked in a stacking direction, and a temperature sensor configured to measure a temperature of at least one power storage cell to be measured among the power storage cells. Each of the power storage cells includes a positive electrode that includes a first current collector, and a positive electrode active material layer, a negative electrode that includes a second current collector, and a negative electrode active material layer, a separator that is arranged between the positive electrode and the negative electrode, and a sealing portion—that surrounds and seals the positive electrode active material layer and the negative electrode active material layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: August 24, 2023
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI,
    Inventors: Hirokuni AKIYAMA, Ryusuke HASE, Satoshi YAMAMOTO, Tomoyuki ITO, Yuki OKAMOTO
  • Patent number: 11737341
    Abstract: According to one embodiment, a detection device comprises a base, a sensor layer, a collimator, a plurality of lenses, and a spacer. The sensor layer is placed on the base and includes a plurality of sensors which output detection signals corresponding to incident light. The collimator layer is placed on the sensor layer and includes a collimator having a plurality of openings which overlap the sensors, respectively. The plurality of lenses are placed on the collimator layer and overlap the openings, respectively. The spacer protrudes more than the lenses in a stacking direction of the base, the sensor layer and the collimator layer.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: August 22, 2023
    Assignee: Japan Display Inc.
    Inventors: Tomoyuki Ito, Jin Hirosawa
  • Publication number: 20230251421
    Abstract: An optical transmission module includes a photonic integrated circuit, a processor that controls the power state of the photonic integrated circuit, and a current source circuit that supplies electric current to a light source used for the photonic integrated circuit. The photonic integrated circuit has an optical multiplexer block including a plurality of multiplexers connected in a n-level tree structure (n is an integer greater than 1), 2{circumflex over (?)}n optical modulators connected to inputs of the optical multiplexer block, and a photodetector connected to an input or an output of each of the plurality of the multiplexers. The light source emits a light beam to be incident onto a corresponding one of the 2{circumflex over (?)}n optical multiplexers. The processor controls the current source circuit for each of the plurality of the multiplexers, based on the monitored value acquired from the photodetector provided to each of the plurality of the multiplexers.
    Type: Application
    Filed: December 21, 2022
    Publication date: August 10, 2023
    Applicant: Fujitsu Optical Components Limited
    Inventors: Yuki YASUDA, Tetsuo ISHIZAKA, Tomoyuki ITO, KENTA NOGAWA, TOSHIO ISHII
  • Publication number: 20230253506
    Abstract: According to one embodiment, a semiconductor device includes a first gate electrode formed to be integrated with a scanning line, an oxide semiconductor layer, a first signal line and a second signal line in contact with the oxide semiconductor layer, and a second gate electrode disposed opposing the first gate electrode with the oxide semiconductor layer interposed therebetween, and connected to the first gate electrode, wherein the second gate electrode does not overlap the first signal line, but overlaps the second signal line.
    Type: Application
    Filed: February 2, 2023
    Publication date: August 10, 2023
    Applicant: Japan Display Inc.
    Inventors: Ryo ONODERA, Akihiro HANADA, Takuo KAITOH, Tomoyuki ITO
  • Patent number: 11721765
    Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: August 8, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Hajime Watakabe, Tomoyuki Ito, Toshihide Jinnai, Isao Suzumura, Akihiro Hanada, Ryo Onodera
  • Patent number: 11710340
    Abstract: A photodiode array is provided and includes insulating substrate; photodiodes arrayed in detection region of insulating substrate, photodiodes configured to output signal in accordance with light incident on photodiodes; first switching elements corresponding to photodiodes and including first semiconductor made of oxide semiconductor; gate lines coupled with first switching elements and extending in first direction; signal lines coupled with first switching elements and extending in second direction intersecting first direction; and gate line drive circuit including second switching element that includes second semiconductor made of polycrystalline silicone, gate line drive circuit being provided in peripheral region outside detection region and configured to drive gate lines, wherein photodiodes includes translucent conductive layer that is cathode, and translucent conductive layer overlaps none of signal lines in plan view.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: July 25, 2023
    Assignee: Japan Display Inc.
    Inventors: Makoto Uchida, Takanori Tsunashima, Masahiro Tada, Tomoyuki Ito, Takashi Nakamura
  • Patent number: 11657549
    Abstract: An information processing apparatus includes a display control section that displays a relation diagram expressing logical relationships between events from an upstream side to a downstream side, displays, in a case where an instruction of folding is performed on a plurality of events selected as folding starting points from among the events, the relation diagram in which events on the downstream side of the plurality of selected events are folded, and displays, in a case where an instruction of expanding is performed on the relation diagram in a folded state, the relation diagram expanded in a state before the folding.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 23, 2023
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Tomoyuki Ito, Hirokazu Mukai, Masato Ando, Minoru Kasama
  • Publication number: 20230127181
    Abstract: According to one embodiment, an optical sensor includes a display panel and a sensor panel under at least a part of the display panel. The display panel includes pixels arranged two-dimensionally. The sensor panel includes a sensor layer including sensor elements arranged two-dimensionally, a collimator layer on the sensor layer including openings, and lenses on the collimator layer. A first number of openings in the openings are on one of the sensor elements. The first number of lenses in the lenses are on the first number of openings. The first number of lenses are at positions different for each of the sensor elements.
    Type: Application
    Filed: October 27, 2022
    Publication date: April 27, 2023
    Applicant: Japan Display Inc.
    Inventor: Tomoyuki ITO
  • Patent number: 11573449
    Abstract: According to one embodiment, a display device comprises a collimating layer including first to third openings, first to third color filters overlaid on the first to third openings, respectively, a first sensor outputting a first detection signal corresponding to light made incident through the first opening and the first color filter, a second sensor outputting a second detection signal corresponding to light made incident through the second opening and the second color filter, and a third sensor outputting a third detection signal corresponding to light made incident through the third opening and the third color filter.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 7, 2023
    Assignee: Japan Display Inc.
    Inventors: Tomoyuki Ito, Kazuki Matsunaga, Shigesumi Araki, Kazuhide Mochizuki