Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to perform a write operation on the non-volatile memory in response to a write command from a host by writing system data in a first mode to a first block of the non-volatile memory, the first mode being a write mode for writing data with a first number of bits per memory cell, writing user data in the first mode to a second block of the non-volatile memory when the write command is of a first type, and writing user data in a second mode to a third block of the non-volatile memory when the write command is of a second type. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.

Abstract: A memory system includes a memory controller configured to write data in a first mode to a first block of a first area of a non-volatile memory. The first mode is a write mode for writing data with a first number of bits per memory cell. The memory controller is further configured to execute copy processing on the data written in the first mode to the first block, by writing system data written in the first block to a second block of the first area in the first mode and writing user data written in the first block to a third block of a second area of the non-volatile memory in the second mode. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.

Abstract: A memory system includes a memory controller configured to write data in a first mode to a first block of a first area of a non-volatile memory. The first mode is a write mode for writing data with a first number of bits per memory cell. The memory controller is further configured to execute copy processing on the data written in the first mode to the first block, by writing system data written in the first block to a second block of the first area in the first mode and writing user data written in the first block to a third block of a second area of the non-volatile memory in the second mode. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

Abstract: According to one embodiment, a memory system includes first and second memory chips. The first memory chip has a first plane with a first block and a second block and a second plane with a third block and a fourth block. The second memory chip has a third plane with a fifth block and a sixth block and a fourth plane with a seventh block and an eighth block. The memory controller sets the first and third blocks as a first block unit in a user data storage area and the fifth and seventh blocks as a second block unit in the user data storage area. The memory controller allocates the second block, the fourth block, the sixth block, and the eighth block to a management data storage area. The memory controller manages user data operations for accessing the user data storage area in block units.

Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.

Abstract: According to one embodiment, a memory system includes first and second memory chips. The first memory chip has a first plane with a first block and a second block and a second plane with a third block and a fourth block. The second memory chip has a third plane with a fifth block and a sixth block and a fourth plane with a seventh block and an eighth block. The memory controller sets the first and third blocks as a first block unit in a user data storage area and the fifth and seventh blocks as a second block unit in the user data storage area. The memory controller allocates the second block, the fourth block, the sixth block, and the eighth block to a management data storage area. The memory controller manages user data operations for accessing the user data storage area in block units.

Abstract: According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.

Abstract: According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.

Abstract: A memory system connectable to a host includes a nonvolatile memory that includes a plurality of blocks, and a controller that is electrically connected to the nonvolatile memory. The controller is configured to determine whether or not write data received from the host has system data characteristics based on tag information received from the host along with the write data, and to write first write data designated as data having the system data characteristics according to the received tag information into a first block for writing first type data having a first level update frequency, and write second write data not designated as data having the system data characteristics according to the received tag information into a second block for writing second type data having a second level update frequency lower than the first level update frequency.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

Abstract: A semiconductor memory device includes a memory unit configured in page units, an error correction code (ECC) module for generating error correcting codes, a page information addition module for generating page information, and a controller for controlling the reading and writing of data to the memory unit. The controller is configured to associate error correction code information and page information with each frame unit of data written to the memory unit and to store the associated information with each frame unit. The controller is configured to output data to an external host in sizes less than one page unit, such as one frame unit.

Abstract: A semiconductor memory device includes a memory unit configured in page units, an error correction code (ECC) module for generating error correcting codes, a page information addition module for generating page information, and a controller for controlling the reading and writing of data to the memory unit. The controller is configured to associate error correction code information and page information with each frame unit of data written to the memory unit and to store the associated information with each frame unit. The controller is configured to output data to an external host in sizes less than one page unit, such as one frame unit.