Patents by Inventor Tomoyuki Katou

Tomoyuki Katou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gateway apparatus and data transfer control method
    Patent number: 8265087
    Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: September 11, 2012
    Assignees: Fujitsu Ten Limited, Fujitsu Semiconductor Limited, Renesas Electronics Corporation
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Error detector and error detection method
    Patent number: 8122316
    Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: February 21, 2012
    Assignees: Fujitsu Ten Limited, Fujitsu Semiconductor Limited, Renesas Electronics Corporation
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Gateway apparatus and data managing method
    Patent number: 8027352
    Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: September 27, 2011
    Assignees: Fujitsu Semiconductor Limited, Renesas Technology Corporation
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Error detector and error detection method
    Publication number: 20080141074
    Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
    Type: Application
    Filed: October 25, 2007
    Publication date: June 12, 2008
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORP.
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Gateway apparatus and data managing method
    Publication number: 20080101393
    Abstract: A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 1, 2008
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORP.
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Gateway apparatus and data transfer control method
    Publication number: 20080101394
    Abstract: A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 1, 2008
    Applicants: FUJITSU TEN LIMITED, FUJITSU LIMITED, RENESAS TECHNOLOGY CORPORATION
    Inventors: Kaoru Noumi, Susumu Nishihashi, Tomoyuki Katou, Yukio Ishikawa, Yasuyuki Umezaki, Hidetaka Ebeshu, Shigeo Koide, Yukio Fujisawa, Hiroaki Shimauchi
  • Passenger car
    Patent number: D735078
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: July 28, 2015
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Sou Tamiya, Shinichi Imai, Tomoyuki Katou