Patents by Inventor Tomoyuki Kida

Tomoyuki Kida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6314332
    Abstract: In a semiconductor device test apparatus, a host computer having a data base writes test resultant data in the data base to output the test resultant data in response to a data request. Each of a plurality of testers performs an electric characteristic test based on a test program to generate a test resultant data for each of semiconductor devices to transmit to the host computer. Each of a plurality of handler sections sets the semiconductor devices of a pallet to a test head for the electric characteristic test. A loader section loads the semiconductor devices from a first tray to the pallet. An unloader section unloads the semiconductor devices from the pallet transported thereto to second trays based on the test resultant data from the host computer.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kida
  • Patent number: 6171350
    Abstract: An apparatus that performs a process wherein the lines representing the lead rows on the four sides, respectively, of an electronic part 322 are calculated. The diagonals of the rectangle formed from these lines and the intersection angle between these diagonals are used as the base lines and base point of the electronic part. Likewise the lines representing the outer-end rows of the bonding pads of p.c. board 320 are calculated. The diagonals of the rectangle defined by these lines and the intersection angle between these diagonals are used as the base lines and base point of the p.c. board. Subsequently correction of the angle and position is carried out based on the corrective amounts of the average intersection angle &thgr;e between both base lines and the coordinate differences Xe and Ye between both base points to align precisely electronic part 322 with p.c. board 320, thus the implementation being possible to be completed.
    Type: Grant
    Filed: July 19, 1994
    Date of Patent: January 9, 2001
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kida
  • Patent number: 5512842
    Abstract: An inspection method and apparatus of semiconductor integrated circuits, in which a specification, a measuring system error in measurements and a number N of measurement repeat times are read in and a distance between parts of the semiconductor integrated circuit is measured to obtain measured value. The measured value is compared with the specification to execute a first non-defective/defective discrimination. The measured value determined to be defective by the first discrimination is further compared with a new discrimination reference obtained by adding the measuring system error to the specification to execute a second non-defective/defective discrimination. Against the semiconductor integrated circuits discriminated to be defective in the first discrimination and to be non-defective in the second discrimination, the measurement is carried out N times and an average value of the N number of measured values is calculated.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: April 30, 1996
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kida
  • Patent number: 5412477
    Abstract: A lead-bend measuring apparatus comprising: an illuminating device for projecting light onto leads projecting from a package of an integrated circuit device; an imaging device for imaging light reflected from and transmitted through the leads; a cutout device for fetching an image of the imaged light and dividing the image into a plurality of sections; a binarization processing device for processing gradations of the image with different binarization levels for each of the divided sections; a profile counter device for preparing profiles of various portions of the leads corresponding to the respective sections from binarized data subjected to processing by the binarization processing device; a calculating device for calculating a deviation of each of the prepared profiles from a reference profile and determining an amount of bend of each of the leads; and a device for determining a non-defective or defective state by making a comparison between the amount of bend calculated and allowable values.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: May 2, 1995
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kida
  • Patent number: 5268743
    Abstract: A single-axle stage is moved in a direction from B to A while measuring the distance between a laser array displacement meter and an outer lead of a tape carrier package, and after completion of measurement in such a direction, a rotary stage is turned clockwise by 90 degrees and the single-axle stage is similarly moved in a direction from C to B, to collect data on the distance between the laser array displacement meter and each of outer leads which are enough to recognize the shape of each outer lead and to store them in an internal memory disposed in a CPU. The flatness of each outer lead is determined by calculating based upon these data a regression line for each outer lead and the maximum scatter amount of data in regard to the regression line by a single lead flatness operating unit. The flatness of each side of the tape carrier package is determined by performing a similar operation from similar data on one side by a one-side flatness operating unit.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: December 7, 1993
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kida
  • Patent number: 5249239
    Abstract: A coplanarity measuring apparatus includes an image converting section, an optical lens mechanism, an image processing section, and an arithmetic operating section. The image converting section converts a transmission image of lead end portions of a surface-mount type IC package into image data. The optical lens mechanism vertically enlarges a transmission image, of the lead end portions, which is projected by the image converting section, and horizontally reduces the vertically enlarged transmission image. The image processing section converts the image data output from the image converting section into binary data and forming a profile. The arithmetic operating section calculates a coplanarity from the profile formed by the image processing section and checks whether a product is defective.
    Type: Grant
    Filed: July 15, 1991
    Date of Patent: September 28, 1993
    Assignee: NEC Corporation
    Inventor: Tomoyuki Kida