Patents by Inventor Tomoyuki Kirimura
Tomoyuki Kirimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10658293Abstract: A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.Type: GrantFiled: December 26, 2018Date of Patent: May 19, 2020Assignee: SOCIONEXT INC.Inventor: Tomoyuki Kirimura
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Publication number: 20190131239Abstract: A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Applicant: SOCIONEXT INC.Inventor: Tomoyuki Kirimura
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Patent number: 10204858Abstract: A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.Type: GrantFiled: October 17, 2017Date of Patent: February 12, 2019Assignee: SOCIONEXT INC.Inventor: Tomoyuki Kirimura
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Publication number: 20180114755Abstract: In a semiconductor device, a plurality of first wirings (X-direction) include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) include a third (fourth) power supply line that is located above the first (second) power supply line and electrically connected to the first (second) power supply line, and a plurality of second wirings (Y-direction) include a first (second) connection wiring that is located above the first (second) power supply line and below the third (fourth) power supply line and electrically connected to the first (second) power supply line and to the third (fourth) power supply line.Type: ApplicationFiled: October 17, 2017Publication date: April 26, 2018Applicant: Socionext Inc.Inventor: Tomoyuki Kirimura
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Patent number: 8703606Abstract: When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask.Type: GrantFiled: February 1, 2012Date of Patent: April 22, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Tomoyuki Kirimura
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Patent number: 8536051Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.Type: GrantFiled: June 13, 2011Date of Patent: September 17, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Hikaru Ohira, Tomoyuki Kirimura
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Patent number: 8466518Abstract: A semiconductor device manufacturing method includes forming a first stopper film and a second stopper film over a first stress film; etching, with a first mask covering a first region and with the first stopper film, the second stopper film in a second region while side-etching the second stopper film in a part of the first region near the second region; forming a second stress film whose etching characteristic is different from the second stopper film; etching, with a second mask covering the second region and having an end face located over the second stopper film and with the second stopper film, the second stress film so that a part of the second stress film overlaps a part of the first stress film and a part of the second stopper film; and forming a contact hole down to the gate interconnect.Type: GrantFiled: May 2, 2011Date of Patent: June 18, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Tomoyuki Kirimura
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Patent number: 8362569Abstract: A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor.Type: GrantFiled: April 16, 2010Date of Patent: January 29, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Tomoyuki Kirimura, Jusuke Ogura
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Publication number: 20120129338Abstract: When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tomoyuki Kirimura
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Publication number: 20120070974Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.Type: ApplicationFiled: June 13, 2011Publication date: March 22, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hikaru Ohira, Tomoyuki Kirimura
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Publication number: 20120038000Abstract: A semiconductor device manufacturing method includes forming a first stopper film and a second stopper film over a first stress film; etching, with a first mask covering a first region and with the first stopper film, the second stopper film in a second region while side-etching the second stopper film in a part of the first region near the second region; forming a second stress film whose etching characteristic is different from the second stopper film; etching, with a second mask covering the second region and having an end face located over the second stopper film and with the second stopper film, the second stress film so that a part of the second stress film overlaps a part of the first stress film and a part of the second stopper film; and forming a contact hole down to the gate interconnect.Type: ApplicationFiled: May 2, 2011Publication date: February 16, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tomoyuki Kirimura
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Publication number: 20100270623Abstract: A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor.Type: ApplicationFiled: April 16, 2010Publication date: October 28, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Tomoyuki Kirimura, Jusuke Ogura