Patents by Inventor Tomoyuki Myojin

Tomoyuki Myojin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914507
    Abstract: To make validity of a prediction model created by machine learning be able to be verified with appropriate accuracy and efficiency. A software test apparatus includes a storage device configured to store a prediction model, and an arithmetic device. The arithmetic device is configured to accept inputs of a precondition, a constraint condition, and an approximation threshold value, convert the prediction model into a logical expression, analyze an approximation range based on the approximation threshold value with respect to the logical expression to simplify the logical expression, generate an inspection expression by combining the simplified logical expression with the precondition and negation of the constraint condition, search for, as a counterexample, a value satisfying the inspection expression, input the value to the prediction model to evaluate inspection accuracy when the counterexample exists, and output a result of the evaluation.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 27, 2024
    Assignee: HITACHI, LTD.
    Inventors: Hironobu Kuruma, Naoto Sato, Tomoyuki Myojin, Hideto Ogawa, Makoto Ishikawa
  • Publication number: 20220391315
    Abstract: To make validity of a prediction model created by machine learning be able to be verified with appropriate accuracy and efficiency. A software test apparatus includes a storage device configured to store a prediction model, and an arithmetic device. The arithmetic device is configured to accept inputs of a precondition, a constraint condition, and an approximation threshold value, convert the prediction model into a logical expression, analyze an approximation range based on the approximation threshold value with respect to the logical expression to simplify the logical expression, generate an inspection expression by combining the simplified logical expression with the precondition and negation of the constraint condition, search for, as a counterexample, a value satisfying the inspection expression, input the value to the prediction model to evaluate inspection accuracy when the counterexample exists, and output a result of the evaluation.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 8, 2022
    Applicant: Hitachi, Ltd.
    Inventors: Hironobu KURUMA, Naoto SATO, Tomoyuki MYOJIN, Hideto OGAWA, Makoto ISHIKAWA
  • Publication number: 20220222552
    Abstract: To efficiently verify and improve a robustness of a learning model for supervised machine learning. A data-creation assistance apparatus 100 includes: a storage device 101 configured to store a neural network model 110 and test data 120; and a computing device 104 configured to specify an uncertainty of an inference result acquired by the neural network model 110; acquire gradient information of the test data 120 by a back propagation process using the uncertainty as a loss; apply various minute changes to the test data 120 to generate a plurality of minutely changed test data, and calculate deviations between each of the plurality of pieces minutely changed test data and the test data 120; and specify, based on the uncertainty information, the gradient information, and the deviations, a minute change that increases or decreases the uncertainty.
    Type: Application
    Filed: December 14, 2021
    Publication date: July 14, 2022
    Applicant: HITACHI, LTD.
    Inventors: Tomoyuki Myojin, Hironobu Kuruma, Naoto Sato, Hideto Ogawa
  • Patent number: 11080173
    Abstract: The boundary search test support device includes: a storage device that holds a plurality of input vectors; and an arithmetic device that executes a test by sequentially inputting the input vectors to a program generated by a neural network and acquiring output vectors which are test results, respectively generates, in a coordinate system which takes each of a predetermined plurality of elements among elements constituting the output vectors as a coordinate axis, a straight line in which the plurality of elements has a same value and a hyperplane in which a sum of values of the plurality of elements is taken as a predetermined value, and arranges a most antagonistic point and boundary vectors whose values of the elements rank higher than or equal to a predetermined ranking among the output vectors in the coordinate system, and outputs the coordinate system together with input vectors corresponding to the boundary vectors.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 3, 2021
    Assignee: HITACHI, LTD.
    Inventors: Naoto Sato, Tomoyuki Myojin, Hironobu Kuruma, Yuichiroh Nakagawa, Hideto Noguchi
  • Patent number: 11055210
    Abstract: Software test equipment including a data conversion unit receives test input data to convert the test input data into software input data to be provided to software and model input data, a software execution unit receives the software input data, executes the test target software based on the software input data, and outputs an execution result, a model execution unit receives a reference model for the software to generate a model allowable output value range of the execution result obtained by executing the software, based on the model input data and the reference model, a difference analysis unit generates difference information based on the execution result output by the software execution unit and the model allowable output value range generated by the model execution unit, and an evaluation unit receives evaluation criteria and evaluates the behavior of the software based on the difference information and the evaluation criteria.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 6, 2021
    Assignee: HITACHI, LTD.
    Inventors: Hironobu Kuruma, Hideto Ogawa, Yuichiroh Nakagawa, Shinji Itoh, Naoto Sato, Tomoyuki Myojin
  • Patent number: 10789155
    Abstract: A coverage test support device includes a memory device that stores a test case and specification content of each of a plurality of coverage indexes, and an arithmetic device that sequentially gives a test input value of each pair in the test case to a program created by a neural network, executes a predetermined number of tests, and acquires a test result of the tests and neuron information at the time of test execution, applies the acquired neuron information to the specification content of each coverage indexes and calculates a value for each coverage index, and identifies, among the coverage indexes, a coverage index in which an elongation rate of the calculated value shows a predetermined tendency, as a preferential coverage index that is to be used preferentially, when either the number of executions of the tests or the number of bugs in the test result exceeds a predetermined standard.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 29, 2020
    Assignee: HITACHI, LTD.
    Inventors: Naoto Sato, Tomoyuki Myojin, Yuichiroh Nakagawa, Hironobu Kuruma, Hideto Noguchi
  • Publication number: 20190220388
    Abstract: The boundary search test support device includes: a storage device that holds a plurality of input vectors; and an arithmetic device that executes a test by sequentially inputting the input vectors to a program generated by a neural network and acquiring output vectors which are test results, respectively generates, in a coordinate system which takes each of a predetermined plurality of elements among elements constituting the output vectors as a coordinate axis, a straight line in which the plurality of elements has a same value and a hyperplane in which a sum of values of the plurality of elements is taken as a predetermined value, and arranges a most antagonistic point and boundary vectors whose values of the elements rank higher than or equal to a predetermined ranking among the output vectors in the coordinate system, and outputs the coordinate system together with input vectors corresponding to the boundary vectors.
    Type: Application
    Filed: January 11, 2019
    Publication date: July 18, 2019
    Inventors: Naoto SATO, Tomoyuki MYOJIN, Hironobu KURUMA, Yuichiroh NAKAGAWA, Hideto NOGUCHI
  • Publication number: 20190196943
    Abstract: A coverage test support device includes a memory device that stores a test case and specification content of each of a plurality of coverage indexes, and an arithmetic device that sequentially gives a test input value of each pair in the test case to a program created by a neural network, executes a predetermined number of tests, and acquires a test result of the tests and neuron information at the time of test execution, applies the acquired neuron information to the specification content of each coverage indexes and calculates a value for each coverage index, and identifies, among the coverage indexes, a coverage index in which an elongation rate of the calculated value shows a predetermined tendency, as a preferential coverage index that is to be used preferentially, when either the number of executions of the tests or the number of bugs in the test result exceeds a predetermined standard.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Applicant: HITACHI, LTD.
    Inventors: Naoto SATO, Tomoyuki MYOJIN, Yuichiroh NAKAGAWA, Hironobu KURUMA, Hideto NOGUCHI
  • Publication number: 20190121722
    Abstract: Software test equipment including a data conversion unit receives test input data to convert the test input data into software input data to be provided to software and model input data, a software execution unit receives the software input data, executes the test target software based on the software input data, and outputs an execution result, a model execution unit receives a reference model for the software to generate a model allowable output value range of the execution result obtained by executing the software, based on the model input data and the reference model, a difference analysis unit generates difference information based on the execution result output by the software execution unit and the model allowable output value range generated by the model execution unit, and an evaluation unit receives evaluation criteria and evaluates the behavior of the software based on the difference information and the evaluation criteria.
    Type: Application
    Filed: September 12, 2018
    Publication date: April 25, 2019
    Applicant: HITACHI, LTD.
    Inventors: Hironobu KURUMA, Hideto OGAWA, Yuichiroh NAKAGAWA, Shinji ITOH, Naoto SATO, Tomoyuki MYOJIN
  • Patent number: 9497493
    Abstract: A video communication system having: an encoder coding input video data and outputting a video stream; and a packet processing part grouping into packets the output video stream from said encoder and outputting the same to a communication path; wherein said packet processing part generates an original data cluster consolidating a packet for each group of a prescribed number of MB processes and redundant data for correcting data errors of said original data cluster; and controls the insertion quantity of redundant data so that the combined number of bits of said original data cluster and said redundant data works out to be equal to or less than the target number of bits.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: November 15, 2016
    Assignee: Hitachi Maxell, Ltd.
    Inventors: Mitsuhiro Okada, Hironori Komi, Taku Nakamura, Tomoyuki Myojin, Hiroki Mizosoe, Yusuke Yatabe
  • Patent number: 8600177
    Abstract: A refresh area is taken advantage of when a series of images are coded using Intra-frame coding and Inter-frame coding, a partial area of an image being forcefully Intra-frame coded (Intra MBs) in the refresh area. As the prediction mode for prediction of the Intra MBs inside the refresh area, a prediction mode is selected where the prediction is executable based on only the image that exists inside the refresh area.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: December 3, 2013
    Assignee: Hitachi Consumer Electronics Co., Ltd
    Inventors: Yusuke Yatabe, Hironori Komi, Mitsuhiro Okada, Tomoyuki Myojin, Hiroki Mizosoe
  • Publication number: 20110247033
    Abstract: A video communication system having: an encoder coding input video data and outputting a video stream; and a packet processing part grouping into packets the output video stream from said encoder and outputting the same to a communication path; wherein said packet processing part generates an original data cluster consolidating a packet for each group of a prescribed number of MB processes and redundant data for correcting data errors of said original data cluster; and controls the insertion quantity of redundant data so that the combined number of bits of said original data cluster and said redundant data works out to be equal to or less than the target number of bits.
    Type: Application
    Filed: November 29, 2010
    Publication date: October 6, 2011
    Inventors: Mitsuhiro Okada, Hironori Komi, Taku Nakamura, Tomoyuki Myojin, Hiroki Mizosoe, Yusuke Yatabe
  • Publication number: 20110243468
    Abstract: A refresh area is taken advantage of when a series of images are coded using Intra-frame coding and Inter-frame coding, a partial area of an image being forcefully Intra-frame coded (Intra MBs) in the refresh area. As the prediction mode for prediction of the Intra MBs inside the refresh area, a prediction mode is selected where the prediction is executable based on only the image that exists inside the refresh area.
    Type: Application
    Filed: November 23, 2010
    Publication date: October 6, 2011
    Inventors: Yusuke Yatabe, Hironori Komi, Mitsuhiro Okada, Tomoyuki Myojin, Hiroki Mizosoe
  • Publication number: 20110235929
    Abstract: An image encoding method for encoding an image using intra coding and interframe coding is offered. A refreshing area in which image refreshing is performed by intra coding is established. The refreshing area is shifted in an equal increment every frame such that the refreshing area traverses through the whole frame periodically. Where a macroblock that have passed through the refreshing area is interframe coded, a motion compensation vector of the macroblock is selected such that an image which has passed through the refreshing area is referenced.
    Type: Application
    Filed: October 21, 2010
    Publication date: September 29, 2011
    Inventors: Hiroki MIZOSOE, Hironori Komi, Yusuke Yatabe, Tomoyuki Myojin, Mitsuhiro Okada