Patents by Inventor Tomoyuki Okawa
Tomoyuki Okawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8540578Abstract: A network game system and a client game device increase the attraction and strengthening of friendships between players. The network game system includes game devices, each of which includes a unit that reads out a player ID from an external storage medium, and a server terminal that is communicably connected to the game devices through a network. Presentation process information is used for performing a game presentation associated with a game presentation ID at the time of performing a game and is stored in a managing section. The game presentation ID is set to be used in the external storage medium based on the player ID and is stored in the managing section in association with the player ID. When a predetermined condition is satisfied, information on the use permission setting of the game presentation ID that is stored in the managing section is updated.Type: GrantFiled: June 22, 2009Date of Patent: September 24, 2013Assignee: Sega CorporationInventors: Kaori Kobayashi, Tomoyuki Okawa, Hideya Takahashi
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Patent number: 8065496Abstract: To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data 0 stored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG. 1(1). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data 0 (for example, entry 1) from the LRU information as a candidate for the LRU control, based on the storage data 0 as the ID of the entry with the oldest last use time.Type: GrantFiled: August 27, 2008Date of Patent: November 22, 2011Assignee: Fujitsu LimitedInventors: Tomoyuki Okawa, Hiroyuki Kojima, Masaki Ukai
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Patent number: 8060698Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.Type: GrantFiled: July 15, 2008Date of Patent: November 15, 2011Assignee: Fujitsu LimitedInventors: Souta Kusachi, Kuniki Morita, Masaki Ukai, Tomoyuki Okawa
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Patent number: 8006139Abstract: A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.Type: GrantFiled: August 26, 2008Date of Patent: August 23, 2011Assignee: Fujitsu LimitedInventors: Tomoyuki Okawa, Kuniki Morita
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Publication number: 20110151969Abstract: By assigning presentation process information, which is used for changing a game screen or a game sound to a game screen or a game sound that is different from an ordinary game screen or game sound, to a player through an external storage medium when a predetermined condition is satisfied, a network game system and a client game device capable of increasing the attraction and strengthening the friendship between players are provided.Type: ApplicationFiled: June 22, 2009Publication date: June 23, 2011Inventors: Kaori Kobayashi, Tomoyuki Okawa, Hideya Takahashi
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Patent number: 7743215Abstract: A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.Type: GrantFiled: October 31, 2007Date of Patent: June 22, 2010Assignee: Fujitsu LimitedInventors: Tomoyuki Okawa, Hiroyuki Kojima, Hideki Sakata, Masaki Ukai
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Patent number: 7636811Abstract: A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space, and a tag received from the storage unit.Type: GrantFiled: November 24, 2004Date of Patent: December 22, 2009Assignee: Fujitsu LimitedInventors: Tomoyuki Okawa, Mie Tonosaki, Masaki Ukai
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Publication number: 20080320327Abstract: A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.Type: ApplicationFiled: August 26, 2008Publication date: December 25, 2008Applicant: FUJITSU LIMITEDInventors: Tomoyuki OKAWA, Kuniki MORITA
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Publication number: 20080320256Abstract: To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data 0 stored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG. 1(1). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data 0 (for example, entry 1) from the LRU information as a candidate for the LRU control, based on the storage data 0 as the ID of the entry with the oldest last use time.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Applicant: FUJITSU LIMITEDInventors: Tomoyuki Okawa, Hiroyuki Kojima, Masaki Ukai
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Publication number: 20080301372Abstract: A memory access control apparatus includes an MIB for storing information on a plurality of requests and processing the requests in parallel. Upon receipt of a memory access request, the MIB selects a request for a data block to be processed corresponding to the same set of a data block to be processed in response to the memory access request, and outputs a WAY assigned to the selected request to a replace-WAY selecting unit. The replace-WAY selecting unit excludes the WAY output from the MIB, and selects a WAY to be assigned to the memory access request based on a predetermined algorithm.Type: ApplicationFiled: July 31, 2008Publication date: December 4, 2008Applicant: FUJITSU LIMITEDInventors: Hiroyuki Kojima, Tomoyuki Okawa
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Publication number: 20080282037Abstract: A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state.Type: ApplicationFiled: July 15, 2008Publication date: November 13, 2008Applicant: FUJITSU LIMITEDInventors: Souta Kusachi, Kuniki Morita, Masaki Ukai, Tomoyuki Okawa
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Patent number: 7428617Abstract: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.Type: GrantFiled: November 30, 2004Date of Patent: September 23, 2008Assignee: Fujitsu LimitedInventors: Tomoyuki Okawa, Kumiko Endo, Hiroyuki Kojima, Masaki Ukai
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Publication number: 20080229011Abstract: A cache memory unit connecting to a main memory system having a cache memory area in which, if memory data that the main memory system has is registered therewith, the registered memory data is accessed by a memory access instruction that accesses the main memory system and a local memory area with which local data to be used by the processing section is registered and in which the registered local data is accessed by a local memory access instruction, which is different from the memory access instruction.Type: ApplicationFiled: March 14, 2008Publication date: September 18, 2008Applicant: FUJITSU LIMITEDInventors: Iwao YAMAZAKI, Tsuyoshi Motokurumada, Hitoshi Sakurai, Hiroyuki Kojima, Tomoyuki Okawa
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Publication number: 20080162818Abstract: A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.Type: ApplicationFiled: October 31, 2007Publication date: July 3, 2008Applicant: Fujitsu LimitedInventors: Tomoyuki Okawa, Hiroyuki Kojima, Hideki Sakata, Masaki Ukai
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Patent number: 7366820Abstract: A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unit 61 outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unit 1A.Type: GrantFiled: November 30, 2004Date of Patent: April 29, 2008Assignee: Fujitsu LimitedInventors: Mie Tonosaki, Tomoyuki Okawa
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Publication number: 20060026352Abstract: A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unit 61 outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unit 1A.Type: ApplicationFiled: November 30, 2004Publication date: February 2, 2006Applicant: FUJITSU LIMITEDInventors: Mie Tonosaki, Tomoyuki Okawa
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Publication number: 20060026356Abstract: A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space, and a tag received from the storage unit.Type: ApplicationFiled: November 24, 2004Publication date: February 2, 2006Applicant: Fujitsu LimitedInventors: Tomoyuki Okawa, Mie Tonosaki, Masaki Ukai
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Publication number: 20060026355Abstract: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.Type: ApplicationFiled: November 30, 2004Publication date: February 2, 2006Applicant: Fujitsu LimitedInventors: Tomoyuki Okawa, Kumiko Endo, Hiroyuki Kojima, Masaki Ukai