Abstract: A semiconductor device 1 including a cell region 2 formed with a semiconductor element 6 and a periphery region 3 formed in the periphery of the cell region 2. The semiconductor region 1 is arranged with an n? type drift region 12 formed in the cell region 2 and periphery region 3, a plurality of p? type columnar regions formed in the n? drift region 12 of the cell region 2, a plurality of p? type columnar resistance improvement regions 23n formed in the n? type drift region 12 of the periphery region 3, and a plurality of electrical field buffer regions 24n formed in an upper part of the p? type columnar region 23n. An interval Sn between the electrical field buffer region 24n and an adjacent electrical field buffer region 24n is different between an interior side and an exterior side of the periphery region 3.

Abstract: A semiconductor device 1 including a cell region 2 formed with a semiconductor element 6 and a periphery region 3 formed in the periphery of the cell region 2. The semiconductor region 1 is arranged with an n? type drift region 12 formed in the cell region 2 and periphery region 3, a plurality of p? type columnar regions formed in the n? drift region 12 of the cell region 2, a plurality of p? type columnar resistance improvement regions 23n formed in the n? type drift region 12 of the periphery region 3, and a plurality of electrical field buffer regions 24n formed in an upper part of the p? type columnar region 23n. An interval Sn between the electrical field buffer region 24n and an adjacent electrical field buffer region 24n is different between an interior side and an exterior side of the periphery region 3.