Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.

Abstract: A film forming apparatus includes a process chamber 2 configured to accommodate a semiconductor wafer W; a worktable 5 disposed inside the process chamber 2 and configured to place the semiconductor wafer W thereon; a showerhead 40 used as a process gas delivery mechanism disposed to face the worktable 5 and configured to delivery a process gas into the process chamber 2; and an exhaust unit 101 configured to exhaust gas from inside the process chamber 2, wherein the showerhead 40 has a gas passage formed therein for supplying the process gas, and an annular temperature adjusting cell 400 formed therein around the gas passage.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.

Abstract: There is provided a film deposition method of depositing a multielement metal oxide film capable of depositing a multielement metal oxide film having a desired composition and a desired thickness in an improved repeatability. A film deposition method deposits a multielement metal oxide film on a surface of a workpiece by a film depositing process including supplying organometallic source gases generated by atomizing a plurality of organometallic compounds into a processing vessel capable of being evacuated. A dummy film deposition process corresponding to at least three cycles of the film deposition process is carried out by placing a dummy workpiece in the processing vessel and supplying the organometallic source gases into the processing vessel immediately before starting the film deposition process for depositing a multielement metal oxide film on the workpiece. Thus a multielement metal oxide film having a desired composition and a desired thickness can be deposited in an improved repeatability.

Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

Abstract: A shower head formed by stacking a shower base, a gas diffusion plate, and a shower plate and supplying material gas and oxidizer gas to a wafer on a loading table through a first gas diffusion part and a second gas diffusion part formed in both faces of the gas diffusion plate, first gas outlets formed in the shower plate and communicating with a first gas diffusion space, and second gas outlets formed in the shower plate and communicating with a second gas diffusion space. A plurality of heat transfer columns fitted closely to the lower surface of the shower base are installed in the first gas diffusion part so that portions therebetween can form the first gas diffusion space, and radiant heat from the loading table is transmitted by the heat transfer columns in the thickness direction of the shower head.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: The present disclosure relates to a post-etch cleaning treatment for a semiconductor device such as a FeRAM. The treatment comprises providing an etchant comprising both a fluorine compound and a chlorine compound, and applying the etchant to the semiconductor device in a wet cleaning process.

Abstract: Processes for etching PZT and/or forming a ferroelectric capacitor with Ir/IrOx electrodes and a PZT ferroelectric layer use a titanium-containing hard mask, a chlorine/oxygen-based plasma, and a hot substrate, typically at about 350 ° C. The processes add a fluorine-containing compound such as CHF3 to the chlorine/oxygen-based plasma for etching of the PZT layer and add nitrogen to improve sidewall profiles when etching Ir layers. The chlorine/oxygen-based plasmas provide good selectivity with high etch rates for Ir and PZT layers and low etch rates for the hard mask.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes evaluating the capacitor stack to determine the efficacy of the sidewall diffusion barrier layer deposition. When evaluating the capacitor stack after etching a masking layer portion of the hard mask, if “ears” are seen on top of the stack, the sidewall diffusion barrier layer is sufficiently thick to provide an adequate sidewall barrier. Evaluation may be performed using a standard or tilt scanning electron microscope, for example.

Abstract: An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG.

Abstract: An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

Abstract: An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

Abstract: A ferroelectric capacitor electrode contact structure comprising an insulator (304) placed over a substrate (302), the insulator (304) containing a source plug (310) and a drain contact (312). An upper plug layer (322) is place over and electrically connected to a drain contact (312). A multi-component oxide layer (324) is placed over an upper plug layer (322). A bottom electrode (326) is placed over a multi-component oxide layer 324. Multi-component oxide layer (324) prevents the silicidation of the bottom electrode (326) of a ferroelectric capacitor electrode contact structure while surprisingly maintaining an ohmic contact from the substrate (302) through the drain contact (312) through the upper plug layer (322) through the multi-component oxide layer (324) to the bottom electrode 326.

Abstract: Ferroelectric memory with one-capacitor/one-transistor cells and a reference cell with double the capacitance plus a sense amplifier for comparing transient currents in resistors at the sense amplifier inputs. The reference cell includes a diode to prevent reference capacitor polarization switching.

Abstract: A ferroelectric capacitor electrode contact structure comprising an insulator (4) placed over a substrate (2) and containing a transistor source (6) and transistor drain (8) between the substrate (2) and the insulator (4). The insulator (4) contains a source plug (10) and a conductive drain plug (12). The transistor source (6) is electrically connected to the source plug (10). The transistor drain (8) is electrically connected to the conductive drain plug (12). A transistor gate (14) is between the source plug (10) and a conductive drain plug (12) and is contained by the insulator (4). Metal wiring (16) is electrically connected to the source plug (10). A barrier film (18) is placed over the insulator (4) and the conductive drain plug (12). The bottom electrode (20) is placed over the barrier film (18). The ferroelectric layer (22) is placed over the bottom electrode (20). The top electrode (24) is placed over the ferroelectric layer (22).