Patents by Inventor Tomoyuki Sakuma
Tomoyuki Sakuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180053820Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.Type: ApplicationFiled: October 4, 2017Publication date: February 22, 2018Inventors: Tomoyuki Sakuma, Shinya Sako, Noboru Yokoyama, Akihiro Shimada
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Patent number: 9812554Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.Type: GrantFiled: January 19, 2016Date of Patent: November 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Sakuma, Shinya Sato, Noboru Yokoyama, Akihiro Shimada
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Patent number: 9691842Abstract: A semiconductor device includes first semiconductor regions of a first conductivity type spaced apart from each other and second semiconductor regions of a second conductivity type between adjacent first semiconductor regions. At least one second semiconductor region includes a void having at least one outer surface with a crystal plane orientation of (100). A third semiconductor region of the second conductivity type is on each second semiconductor region and a fourth semiconductor region of the first conductivity type is on the third semiconductor region. A gate electrode on is disposed on each first semiconductor region to be adjacent to a third semiconductor region via a gate insulation layer.Type: GrantFiled: August 26, 2015Date of Patent: June 27, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Shinya Sato, Tomoyuki Sakuma, Noboru Yokoyama, Shizue Matsuda
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Publication number: 20170062585Abstract: According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.Type: ApplicationFiled: January 19, 2016Publication date: March 2, 2017Inventors: Tomoyuki Sakuma, Shinya Sato, Noboru Yokoyama, Akihiro Shimada
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Publication number: 20170044686Abstract: A semiconductor manufacturing apparatus includes a chamber, a reaction-gas inlet, a gas exhaust port, a rotation unit, a semiconductor wafer holder, a heater, and a purge-gas inlet. The wafer holder includes a first hold region to hold the semiconductor wafer and a second hold region held by the rotation unit. The second hold region surrounds the first hold region. The level of the first hold region and the level of the second hold region differ. A plurality of ventholes is provided to the first hold region so that the ventholes are just below a sidewall of the semiconductor wafer held by the first hold region.Type: ApplicationFiled: October 26, 2016Publication date: February 16, 2017Inventors: Shinya Higashi, Shinya Sato, Tomoyuki Sakuma, Akihiko Osawa, Hiroaki Kobayashi, Osamu Yamazaki, Hiroshi Nishimura
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Patent number: 9536997Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a first direction by portions of the semiconductor layer, each of the first regions including a first semiconductor region of a second conductivity type, a second region between the first regions in the first direction, the second region including a second semiconductor region of the first conductivity type and a first insulator between the second semiconductor region and the semiconductor layer, and a third region between the first region and the second region, the third region including a third semiconductor region of the first conductivity type and a second insulator.Type: GrantFiled: February 29, 2016Date of Patent: January 3, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Noboru Yokoyama, Shinya Sato, Tomoyuki Sakuma
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Publication number: 20160260797Abstract: A semiconductor device includes first semiconductor regions of a first conductivity type spaced apart from each other and second semiconductor regions of a second conductivity type between adjacent first semiconductor regions. At least one second semiconductor region includes a void having at least one outer surface with a crystal plane orientation of (100). A third semiconductor region of the second conductivity type is on each second semiconductor region and a fourth semiconductor region of the first conductivity type is on the third semiconductor region. A gate electrode on is disposed on each first semiconductor region to be adjacent to a third semiconductor region via a gate insulation layer.Type: ApplicationFiled: August 26, 2015Publication date: September 8, 2016Inventors: Shinya SATO, Tomoyuki SAKUMA, Noboru YOKOYAMA, Shizue MATSUDA
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Publication number: 20140283748Abstract: A semiconductor manufacturing apparatus includes a chamber, a reaction-gas inlet, a gas exhaust port, a rotation unit, a semiconductor wafer holder, a heater, and a purge-gas inlet. The wafer holder includes a first hold region to hold the semiconductor wafer and a second hold region held by the rotation unit. The second hold region surrounds the first hold region. The level of the first hold region and the level of the second hold region differ. A plurality of ventholes is provided to the first hold region so that the ventholes are just below a sidewall of the semiconductor wafer held by the first hold region.Type: ApplicationFiled: September 11, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shinya Higashi, Shinya Sato, Tomoyuki Sakuma, Akihiko Osawa, Hiroaki Kobayashi, Osamu Yamazaki, Hiroshi Nishimura
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Patent number: 8097501Abstract: A method for manufacturing a semiconductor device, includes: forming a first-conductivity-type semiconductor region on a semiconductor layer; forming a mask member on the first-conductivity-type semiconductor region; selectively forming an opening in the mask member; etching the first-conductivity-type semiconductor region exposed to the opening to form a trench having a larger diameter than the opening and an eaves-like mask projected above the trench and made of the mask member; and forming a second-conductivity-type semiconductor region in the trench below the eaves-like mask by epitaxial growth to form a structure section in which the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region are alternately repeated in a direction generally parallel to a major surface of the semiconductor layer.Type: GrantFiled: January 21, 2010Date of Patent: January 17, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoyuki Sakuma, Shingo Sato
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Publication number: 20110169081Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first semiconductor layer is formed with a trench. The second semiconductor layer is buried in the trench, and includes a hollow portion. A length of the hollow portion along depth direction of the trench is 5 ?m or less or 15 ?m or more.Type: ApplicationFiled: January 7, 2011Publication date: July 14, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Hironori Ishikawa, Shinya Sato, Hiroyuki Sugaya, Tomoyuki Sakuma
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Publication number: 20100197088Abstract: A method for manufacturing a semiconductor device, includes: forming a first-conductivity-type semiconductor region on a semiconductor layer; forming a mask member on the first-conductivity-type semiconductor region; selectively forming an opening in the mask member; etching the first-conductivity-type semiconductor region exposed to the opening to form a trench having a larger diameter than the opening and an eaves-like mask projected above the trench and made of the mask member; and forming a second-conductivity-type semiconductor region in the trench below the eaves-like mask by epitaxial growth to form a structure section in which the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region are alternately repeated in a direction generally parallel to a major surface of the semiconductor layer.Type: ApplicationFiled: January 21, 2010Publication date: August 5, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoyuki SAKUMA, Shingo SATO