Patents by Inventor Tomoyuki Yokoyama

Tomoyuki Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230111488
    Abstract: A vehicle control apparatus including a camera, a detector acquiring position information of a target based on reflected wave and a microprocessor. The microprocessor is configured to perform estimating a position of the target, based on position information acquired by the camera and the detector, controlling an actuator based on the estimated position, and detecting a predetermined gradient state in which a gradient of a road surface in front of a subject vehicle is an upward gradient of a predetermined degree or more with respect to a road surface at a current position of the subject vehicle and is configured to perform the estimating including estimating the position of the target by lowering a reliability of position information acquired by the camera among position information of the target captured on the road surface in the predetermined gradient state when the predetermined gradient state is detected.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 13, 2023
    Inventors: Tatsuya Konishi, Yuya Kaneda, Kenta Ishii, Tomoyuki Yokoyama
  • Patent number: 10481625
    Abstract: Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: November 19, 2019
    Assignee: ABLIC INC.
    Inventors: Tadashi Kurozo, Tomoyuki Yokoyama
  • Publication number: 20180292854
    Abstract: Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.
    Type: Application
    Filed: June 8, 2018
    Publication date: October 11, 2018
    Inventors: Tadashi KUROZO, Tomoyuki YOKOYAMA
  • Patent number: 10061335
    Abstract: Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: August 28, 2018
    Assignee: ABLIC INC.
    Inventors: Tadashi Kurozo, Tomoyuki Yokoyama
  • Patent number: 9369117
    Abstract: Provided is a voltage regulator which consumes low power and uses an NMOS transistor as an output transistor. A delay circuit includes, between a constant current circuit and a capacitor, a depletion type NMOS transistor having a gate and a back gate each connected to a ground terminal, the constant current circuit including a depletion type NMOS transistor and a resistor connected between each of a gate and a back gate of the depletion type NMOS transistor and a source thereof.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 14, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Yotaro Nihei, Tomoyuki Yokoyama
  • Publication number: 20160112038
    Abstract: Provided is a voltage regulator which consumes low power and uses an NMOS transistor as an output transistor. A delay circuit includes, between a constant current circuit and a capacitor, a depletion type NMOS transistor having a gate and a back gate each connected to a ground terminal, the constant current circuit including a depletion type NMOS transistor and a resistor connected between each of a gate and a back gate of the depletion type NMOS transistor and a source thereof.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Yotaro NIHEI, Tomoyuki YOKOYAMA
  • Publication number: 20140354249
    Abstract: Provided is a voltage regulator having satisfactory transient response characteristics. The voltage regulator includes: a first amplifier for detecting that undershoot occurs in an output voltage; a second amplifier for detecting that overshoot occurs in the output voltage; a first constant current circuit for increasing a bias current of an error amplifier circuit by a first amount for a first time period in response to a signal determined based on one of an output signal of the first amplifier and an output signal of the second amplifier; a second constant current circuit for increasing the bias current of the error amplifier circuit by a second amount larger than the first amount for a second time period shorter than the first time period in response to a signal determined based on the output signal of the first amplifier; and a first switch circuit for pulling up a gate of an output transistor in response to a signal determined based on the output signal of the second amplifier.
    Type: Application
    Filed: May 27, 2014
    Publication date: December 4, 2014
    Applicant: Seiko Instruments Inc.
    Inventors: Tadashi KUROZO, Tomoyuki YOKOYAMA
  • Patent number: 7582849
    Abstract: A thermal head driving method of driving thermal heads is disclosed. The method includes a step of dividing the thermal heads into plural groups, providing for each of the groups a common potential terminal, a step of using a drive circuit to drive the thermal heads of one or more of the groups, and a step of applying an operating voltage to the common potential terminal of said one or more groups driven by the drive circuit.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: September 1, 2009
    Assignee: Fujitsu Component Limited
    Inventors: Sumio Watanabe, Fumio Sakurai, Yukihiro Mori, Norio Endo, Shuko Yamaji, Tomoyuki Yokoyama
  • Publication number: 20070045280
    Abstract: A thermal head driving method of driving thermal heads is disclosed. The method includes a step of dividing the thermal heads into plural groups, providing for each of the groups a common potential terminal, a step of using a drive circuit to drive the thermal heads of one or more of the groups, and a step of applying an operating voltage to the common potential terminal of said one or more groups driven by the drive circuit.
    Type: Application
    Filed: May 24, 2006
    Publication date: March 1, 2007
    Applicant: FUJITSU COMPONENT LIMITED
    Inventors: Sumio Watanabe, Fumio Sakurai, Yukihiro Mori, Norio Endo, Shuko Yamaji, Tomoyuki Yokoyama