Abstract: Disclosed herein is related to a method for treating a symptom associated with senescence in a subject by administering to the subject with an effective amount of corylin and/or neobavaisoflavone, wherein the symptom associated with senescence is loss of muscle strength, muscle weakness, loss of motor coordination, loss of balance, skin wrinkle, or a poor blood biochemical parameter.

Abstract: A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on the chip and located in the through opening.

Abstract: A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on the chip and located in the through opening.

Abstract: A heat sink structure according to the present invention is provided. The heat sink has a through opening extending from the upper surface through to the lower surface. A solder is disposed in the through opening and on the upper and lower surfaces of the heat sink, wherein the portion of the solder in the through opening is connected with the portions of the solder on the upper and lower surfaces.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements. A plurality of bumps of the chip is connected to the interposer. The second sealant seals the bumps. A first glass transition temperature of the first sealant is higher than a second glass transition temperature of the second sealant. Since glass transition temperatures of the first sealant and the second sealant are different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the inner stress will be lowered and the yield is promoted.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: A reinforced semiconductor package (500, 700) with a stiffener (400, 600) is provided. The stiffener is composed of an inner ring (410) disposed on the upper surface (512) of a substrate (510) and surrounding a semiconductor chip (520), and an outer ring (420) also disposed on the upper surface of the substrate but surrounding the inner ring. The inner ring and the outer ring are connected with each other by means of at least one tie bar (430), and cooperatively cover a majority portion of the upper surface of the substrate. Accordingly, the strength and rigidity of the substrate of the present semiconductor package can be reinforced to efficiently prevent warpage thereof.

Abstract: Heat dissipation apparatus applies to a package device on a substrate. The package device has an upper surface, a bottom surface, and a sidewall between the upper and bottom surfaces, in which the bottom surface thermally contacts the substrate through multitudes of conductive bumps. For dissipating heat from the bottom surface, the heat dissipation apparatus includes a first heat-dissipating structure contacting a portion of the bottom surface and a second heat-dissipating structure on the upper surface. With the surrounding association of the first and the second heat-dissipating structures, these structures release heats from the sidewall of the die. Such a heat dissipation apparatus is capable of discharging heat at three dimensions, preventing the conductive bumps from collapsing, and enhancing reliability.

Abstract: A chip manufacturing process is disclosed. A wafer having a passivation layer and at least one bonding pad is provided. The surface of the bonding pad is exposed to a first opening of the passivation layer. A first metal layer is formed on the bonding pad exposed by the first opening. A photoresist having a second opening and a photoresist block disposed in the second opening is formed on the first metal layer. The first metal layer corresponding to the second opening has a first surface, and the first metal layer corresponding to the photoresist block has a second surface. A second metal layer is formed on the first surface, and the photoresist block is removed to expose the second surface. A UBM layer is formed on the second metal layer and the second surface of the first metal layer. Finally, a conductive bump is formed on the UBM layer.

Abstract: A heat sink for conducting a coolant is provided. The heat sink includes a casing and a porous material layer. The porous material layer is disposed inside the casing, and the coolant is conducted into the porous material layer. Moreover, a package structure that dissipates heat by use of a coolant is provided. The package structure includes a carrier, a chip, and the aforementioned heat sink. The chip is disposed on the carrier, and the heat sink is disposed on the carrier or above the chip. The heat dissipation efficiency of the package structure can be improved by the heat sink.

Abstract: An asymmetric bump structure for wafer is provided. First, the wafer includes multi-chip units each of which has an active surface. The asymmetric bump structure includes a conductive surface on the active surface, a conductive structure contacted the portion of the conductive surface and located on the both conductive surface and the active surface, and a conductive material contacted the conductive structure. The conductive material and the conductive structure contacted part of the conductive surface have respective geometric centers which are not on an identical vertical axis.

Abstract: A chip packaging process is provided. First, a cavity is formed on a heat sink. A first encapsulant is formed on the bottom of the cavity. A circuit substrate is disposed over the heat sink. The circuit substrate has an opening that corresponds in position to the cavity. Thereafter, a chip is disposed on the first encapsulant and the chip is electrically connected to the circuit substrate. Finally, a compound is deposited over the first encapsulant and the chip to form a chip package. The chip package is warp resistant and the chip packaging process increases overall production yield.

Abstract: Heat dissipation apparatus applies to a package device on a substrate. The package device has an upper surface, a bottom surface, and a sidewall between the upper and bottom surfaces, in which the bottom surface thermally contacts the substrate through multitudes of conductive bumps. For dissipating heat from the bottom surface, the heat dissipation apparatus includes a first heat-dissipating structure contacting a portion of the bottom surface and a second heat-dissipating structure on the upper surface. With the surrounding association of the first and the second heat-dissipating structures, these structures release heats from the sidewall of the die. Such a heat dissipation apparatus is capable of discharging heat at three dimensions, preventing the conductive bumps from collapsing, and enhancing reliability.

Abstract: A bump structure is applicable for disposing above a semiconductor wafer, which has a plurality of bonding pads and a passivation exposing the bonding pads on which a plurality of patterned under bump metallurgy layers are formed. It is characterized that the bump structure is made of a first bump and a second bump, and the bump structure is disposed on one of the patterned under bump metallurgy layer wherein the second bump covers the first bump and the melting point of the second bump is below the melting point of the first bump. In addition, a manufacturing method of the bump structure is provided.