Abstract: A method for improving the Beta (&bgr;) of a parasitic PNP bipolar junction transistor (BJT) in a conventional CMOS process includes the steps of: providing a P-type substrate having a shallow region corresponding to the P+ electrode of the parasitic PNP BJT and the P+ electrode is located within and in contact with an N-well; forming an electrostatic discharge (ESD) mask layer on the P-type substrate, wherein the mask layer has a pattern exposing an area corresponding to the P+ electrode of the PNP parasitic BJT, and exposing one electrode of an ESD device; and implanting P+ ions to the P-type substrate, thereby deepening a P/N junction of the P+ electrode of the parasitic BJT and the N-well.

Abstract: The gate for at least one transistor is formed on the surface of the semiconductor substrate and the gate is utilized as a mask to form a lightly doped drain of the transistor. A low thermal budget deposition process is performed to form a silicon nitride layer on the surface or the semiconductor substrate. An ion implantation process is performed to implant fluorine atoms into the silicon nitride layer. After that, an etching process is performed to form a spacer in the periphery of the gate. Finally, a source/drain of the transistor is formed. The implanted fluorine atoms bond with the hydrogen atoms and keep them from becoming interface trapped charges. This increases the threshold voltage stability of the transistor.

Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: The gate for at least one transistor is formed on the surface of the semiconductor substrate and the gate is utilized as a mask to form a lightly doped drain of the transistor. A low thermal budget deposition process is performed to form a silicon nitride layer on the surface or the semiconductor substrate. An ion implantation process is performed to implant fluorine atoms into the silicon nitride layer. After that, an etching process is performed to form a spacer in the periphery of the gate. Finally, a source/drain of the transistor is formed. The implanted fluorine atoms bond with the hydrogen atoms and keep them from becoming interface trapped charges. This increases the threshold voltage stability of the transistor.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013 ˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.

Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.

Abstract: A fabrication method of a node contact opening involves forming a first insulating layer on the substrate, in which a bit line, which contacts the substrate, is formed on the first insulating layer. A conformal second insulating layer that serves as an etching stop layer is formed after the formation of bit line. A third insulating layer is then formed to isolate the subsequently formed capacitor and bit line. A pattern mask is formed on the third insulating layer, while a pattern of the pattern mask is transferred into the third insulating layer, so that an opening is formed in the third insulating layer. After the second insulating layer in the opening is removed, a spacer is formed on a sidewall of the opening. With the pattern mask and the spacer serving as an etching mask, the first insulating layer below the bit line is etched until the opening is extended through to the substrate, so that a contact opening is formed.

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Abstract: A method of manufacturing an inter-metal dielectric layer. A substrate having a plurality of wires formed thereon is provided. A portion of the substrate is exposed to form an opening between the wires. The opening is filled with a flowable dielectric material, wherein a surface level of the flowable dielectric material is lower than that of the wires. A plurality of spacers is formed on the sidewall of the wires exposed by the flowable dielectric material. The flowable dielectric material is removed. An anisotropic deposition process with a poor-lateral-filling ability is performed to form a dielectric layer with a void under the spacer over the substrate.

Abstract: A method of fabricating a bit line of a flash memory. A silicon-on-insulator (SOI) has a buried oxide layer therein and a silicon layer thereon. A patterned hard mask layer is formed on the silicon layer. The exposed silicon layer and the buried oxide layer thereunder are removed to form a bit line opening while using the hard mask layer as a mask. A conformal lightly doped polysilicon layer is formed over the substrate. A heavily doped polysilicon layer is formed over the substrate and filling the bit line opening. The lightly doped polysilicon layer and the heavily doped polysilicon layer are removed until arriving at the silicon layer to form a bit line. The hard mask layer is then removed.

Abstract: The invention provides a method for fabricating a lower electrode of the capacitor, which method provides a substrate formed with source/drain (S/D) regions. Landing pads are formed on the substrate for connecting to source/drain regions. A dielectric layer is formed on the substrate to cover the landing pads. A stop layer, an insulating layer, and a mask layer are formed in sequence on the dielectric layer. The insulating layer and the mask layer are patterned to form a capacitor opening that exposes the stop layer, followed by forming a spacer on a sidewall of the capacitor opening. With the patterned mask layer and the spacer serving as an etching mask, the stop layer and the dielectric layer are etched in sequence to form a node contact opening which exposes the landing pad, wherein the capacitor opening and the node contact opening form a damascene contact opening. A conformal conducting layer is formed for filling the damascene contact opening, and planarized by CMP.

Abstract: A fabrication method to increase the gate contact area is described, in which a conformal first sacrificial layer is formed on the silicon substrate and the gate structure. A second sacrificial layer is further formed on the silicon substrate, wherein the surface of the second sacrificial layer is lower than the top of the polysilicon gate by a certain thickness. The exposed sacrificial layer is then removed, followed by forming a conformal silicon layer to cover the silicon substrate. A spacer is further formed on a sidewall of the gate structure. Using the spacer as a mask, the exposed polysilicon layer is removed to form a side-wing polysilicon layer on both sides of the gate to increase the contact area of the gate. The spacer, the second sacrificial layer and the first sacrificial layer are then removed. A silicidation process is further conducted to form a silicide layer on the gate structure and the two side-wing polysilicon layer to lower the gate contact resistance.

Abstract: A fabrication method for shallow trench isolation (STI) is briefly described as follows. A substrate is provided with a patterned mask layer and pad oxide layer formed thereon, so that a first opening, which exposes a part of the substrate, is formed. A shallow trench is then formed in the substrate, followed by filling the shallow trench with a first insulating layer, wherein the surface of the first insulating layer is lower than the surface of the substrate, and a part of the substrate forming the sidewall of the shallow trench is exposed. A part of the mask layer and pad oxide layer is removed to enlarge the first opening, so that a second opening, which exposes a part of the substrate, is formed. A doped region is formed on the exposed part of the substrate, while the second opening and the shallow trench are filled with a second insulating layer. Finally, the mask layer and the pad oxide layer are removed in sequence to complete the manufacture of the STI.

Abstract: A method of fabricating a lower electrode of a capacitor. A sacrificial multilayer is formed on a semiconductor layer. The sacrificial multi-layer is a stack of alternating first and second sacrificial layers. A patterned first mask layer having a first opening above a conductive plug in the semiconductor substrate is formed on the sacrificial multi-layer. A planar spacer is formed on the sidewall of the first opening. A second mask layer is formed to fill the first opening. The planar spacer and the sacrificial multi-layer thereunder are anisotropically etched until the semiconductor substrate is exposed to form a second opening while using the first mask layer and second mask layer as a mask. The first sacrificial layers exposed by the second opening are isotropically etched to form a plurality of recesses. The second opening and the recesses are filled with a conductive material layer. Finally, the first mask layer, second mask layer, and sacrificial multi-layer are removed.

Abstract: A method of forming buried bit lines. A silicon-on-insulator (SOI) substrate includes a silicon base layer, a first insulation layer and an epitaxial silicon layer. A shallow trench isolation (STI) layer that contacts the first insulation layer is formed in the epitaxial silicon layer. A trench that penetrates the STI layer and runs deep into the first insulation layer is formed. A buried bit line is formed inside the trench such that the top surface of the buried bit line is located between the upper and the lower surface of the STI layer. A second insulation layer is next formed over the buried bit line such that the top surface of the second insulation layer is at the same level as the top surface of the epitaxial silicon layer. A plurality of word lines and a plurality of source/drain regions are formed over the substrate and in the epitaxial silicon layer.

Abstract: A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.

Abstract: A low-dielectric constant insulation structure is described in which low-dielectric constant insulation layers and silicon oxide layers are alternately stacked on the substrate to form a stacked insulation layer. A required pattern is then etched in the stacked insulation layer followed by a selective etching to remove a portion of the low dielectric insulation layer to form, starting from the sidewall of the stacked insulation layer and extending inwardly, a plurality of recessed regions. A sputtering deposition and etching-back are further conducted on the sidewall of the stacked insulation layer to form a sidewall spacer to enclose the already formed recessed regions. A plurality of air-gaps is formed in the stacked insulation layer to establish a low dielectric insulation structure.

Abstract: A salicide process is described. The edge of a gate are etched to form a reversed T-shaped gate that is then self-aligned by a silicide film. This etching step can be performed by using a silicon oxynitride layer as an etching mask over the gate.