Abstract: A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.

Abstract: A method is performed to a structure that includes a substrate with first and second regions for logic and RF devices respectively, first fin and first gate structure over the first region, second fin and second gate structure over the second region, and gate spacers over sidewalls of the gate structures. The method includes performing a first etching to the first fin to form a first recess; and performing a second etching to the second fin to form a second recess. The first and second etching are tuned to differ in at least one parameter such that the first recess is shallower than the second recess and a first distance between the first recess and the first gate structure along the first fin lengthwise is smaller than a second distance between the second recess and the second gate structure along the second fin lengthwise.

Abstract: A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.

Abstract: A method is performed to a structure that includes a substrate with first and second regions for logic and RF devices respectively, first fin and first gate structure over the first region, second fin and second gate structure over the second region, and gate spacers over sidewalls of the gate structures. The method includes performing a first etching to the first fin to form a first recess; and performing a second etching to the second fin to form a second recess. The first and second etching are tuned to differ in at least one parameter such that the first recess is shallower than the second recess and a first distance between the first recess and the first gate structure along the first fin lengthwise is smaller than a second distance between the second recess and the second gate structure along the second fin lengthwise.