Patents by Inventor Tong Lei
Tong Lei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10276450Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.Type: GrantFiled: February 10, 2017Date of Patent: April 30, 2019Assignee: Shanghai Huali Microelectronics CorporationInventors: Tong Lei, Yongyue Chen, Haifeng Zhou
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Patent number: 10038078Abstract: A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.Type: GrantFiled: February 10, 2017Date of Patent: July 31, 2018Assignee: Shanghai Huali Microelectronics CorporationInventors: Hailan Yi, Tong Lei, Yongyue Chen
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Publication number: 20180175169Abstract: A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.Type: ApplicationFiled: February 10, 2017Publication date: June 21, 2018Applicant: Shanghai Huali Microelectronics CorporationInventors: Hailan Yi, Tong Lei, Yongyue Chen
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Publication number: 20180174924Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.Type: ApplicationFiled: February 10, 2017Publication date: June 21, 2018Applicant: Shanghai Huali Microelectronics CorporationInventors: Tong Lei, Yongyue Chen, Haifeng Zhou
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Patent number: 9991808Abstract: A cross regulation circuit for multiple outputs, includes an input end and at least two output ends. A first output end of the at least two output ends is connected to a feedback circuit. The feedback circuit is connected to the input end and used for maintaining the output voltage of the first output end by adjusting the input end. A first resistor and a first inductor are sequentially connected in series on the upstream of each of other output ends than the first output end and are used for performing cross regulation. In the cross regulation method of the circuit, simultaneous equations are established through parasitic inductance on any output branch and load thereof as well as parasitic inductance on the first output branch so as to obtain the inductance of the first inductor and the capacitance of the first resistor.Type: GrantFiled: July 7, 2014Date of Patent: June 5, 2018Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Zhi Tong Lei, Yu Meng He, Feng Zhang
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Publication number: 20170126139Abstract: A cross regulation circuit for multiple outputs, includes an input end and at least two output ends. A first output end of the at least two output ends is connected to a feedback circuit. The feedback circuit is connected to the input end and used for maintaining the output voltage of the first output end by adjusting the input end. A first resistor and a first inductor are sequentially connected in series on the upstream of each of other output ends than the first output end and are used for performing cross regulation. In the cross regulation method of the circuit, simultaneous equations are established through parasitic inductance on any output branch and load thereof as well as parasitic inductance on the first output branch so as to obtain the inductance of the first inductor and the capacitance of the first resistor.Type: ApplicationFiled: July 7, 2014Publication date: May 4, 2017Applicant: Siemens AktiengesellschaftInventors: Yu Meng HE, Zhi Tong LEI, Feng ZHANG
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Patent number: 9570562Abstract: A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on the polysilicon gate layer; oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, so as to form a silicon oxide interlayer in the top portion of the polysilicon gate layer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of surface of the polysilicon gate layer; removing the oxide layer and the silicon oxide interlayer, so as to obtain a flat surface of the polysilicon gate layer and avoid a series of problems resulted from the uneven surface in the subsequent processes.Type: GrantFiled: August 12, 2016Date of Patent: February 14, 2017Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Tong Lei, Junhua Yan
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Publication number: 20160300758Abstract: The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer; selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.Type: ApplicationFiled: June 29, 2015Publication date: October 13, 2016Inventors: Tong Lei, Jingxun Fang
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Patent number: 9449872Abstract: The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer, selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.Type: GrantFiled: June 29, 2015Date of Patent: September 20, 2016Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Tong Lei, Jingxun Fang
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Patent number: 8416933Abstract: A method of establishing communication including providing a communication by a sending party to a receiving party, and verifying the sending party's identity by a trusted instrumentality. The trusted instrumentality can be at least the sending party communication controller and is usually both the sending and receiving parties' communication controllers. The communication controllers should be certified and preferably be certified by a mutually trusted communication controller certification authority. Also disclosed is a system for establishing communication.Type: GrantFiled: October 30, 2008Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: John Bryan Hartley, Io Tong Lei, David Muscat
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Patent number: 8233604Abstract: A method and system for automatically routing a call to an identity of multiple identities based on an active presence profile. A subscription message is sent to a user's contact addresses. The contact addresses include identities of the user and indicators of remote servers that manage real time communication systems. A presence document that includes a presence status of a first identity of the user is received. The presence status indicates that the first identity is offline. A registration message is issued to a remote server, resulting in a call redirection from the first identity to a second identity. The second identity is included in an active presence profile and is associated with a computing system that receives the redirected call. If multiple presence profiles of the user are active, a matching algorithm selects a contact address of one of the active presence profiles to determine the call redirection.Type: GrantFiled: September 16, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventor: Io Tong Lei
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Publication number: 20100111276Abstract: A method of establishing communication including providing a communication by a sending party to a receiving party, and verifying the sending party's identity by a trusted instrumentality. The trusted instrumentality can be at least the sending party communication controller and is usually both the sending and receiving parties' communication controllers. The communication controllers should be certified and preferably be certified by a mutually trusted communication controller certification authority. Also disclosed is a system for establishing communication.Type: ApplicationFiled: October 30, 2008Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Bryan Hartley, Io Tong Lei, David Muscat
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Publication number: 20100067679Abstract: A method and system for automatically routing a call to an identity of multiple identities based on an active presence profile. A subscription message is sent to a user's contact addresses. The contact addresses include identities of the user and indicators of remote servers that manage real time communication systems. A presence document that includes a presence status of a first identity of the user is received. The presence status indicates that the first identity is offline. A registration message is issued to a remote server, resulting in a call redirection from the first identity to a second identity. The second identity is included in an active presence profile and is associated with a computing system that receives the redirected call. If multiple presence profiles of the user are active, a matching algorithm selects a contact address of one of the active presence profiles to determine the call redirection.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventor: Io Tong Lei