Patents by Inventor Tong-Min Weng

Tong-Min Weng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230207395
    Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 29, 2023
    Inventors: Tong-Min WENG, Tsung-Han Wu
  • Patent number: 11610823
    Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: March 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tong-Min Weng, Tsung-Han Wu
  • Patent number: 10651296
    Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han Wu, Tong-Min Weng, Chun-Yi Huang, Po-Ching Lee, Chih-Hsuan Hsieh, Shu-Ching Tsai
  • Publication number: 20200066601
    Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Tong-Min WENG, Tsung-Han WU
  • Publication number: 20200035815
    Abstract: Methods of fabricating FinFET devices are provided. The method includes forming a fin over a substrate. The method also includes implanting a first dopant on a top surface of the fin and implanting a second dopant on a sidewall surface of the fin. The first dopant is different from the second dopant. The method further includes forming an oxide layer on the top surface and the sidewall surface of the fin, and forming a gate electrode layer over the oxide layer.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han WU, Tong-Min WENG, Chun-Yi HUANG, Po-Ching LEE, Chih-Hsuan HSIEH, Shu-Ching TSAI
  • Patent number: 10504797
    Abstract: A method for forming a semiconductor device includes steps of: forming at least one gate structure comprising a gate electrode over a substrate, and forming a first dielectric layer of a first dielectric material along a side wall of the at least one gate structure. The first dielectric layer of the first dielectric material includes fluorine doped silicon oxycarbonitride with a doping concentration of fluorine. The dielectric constant of the first dielectric layer is adjusted through the doping concentration of fluorine.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tong-Min Weng, Tsung-Han Wu
  • Patent number: 10256233
    Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Kuan Su, Yu-Hong Pan, Jen-Pan Wang, Tong-Min Weng, Tsung-Han Wu
  • Publication number: 20190067129
    Abstract: A method for forming a semiconductor device includes steps of: forming at least one gate structure comprising a gate electrode over a substrate, and forming a first dielectric layer of a first dielectric material along a side wall of the at least one gate structure. The first dielectric layer of the first dielectric material includes fluorine doped silicon oxycarbonitride with a doping concentration of fluorine. The dielectric constant of the first dielectric layer is adjusted through the doping concentration of fluorine.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tong-Min WENG, Tsung-Han WU
  • Publication number: 20180342502
    Abstract: A method for forming a semiconductor device and the resulting device are provided. At least one capacitor in a first gate structure is formed over a substrate. The at least one capacitor includes a first gate electrode including a first conductive layer, a semiconductor layer including a semiconductor material and a dopant, a dielectric layer disposed between the first gate electrode and the semiconductor layer, and a second conductive layer contacting the semiconductor layer. The at least one resistor includes a third conductive layer and is electrically connected to the at least one capacitor.
    Type: Application
    Filed: January 30, 2018
    Publication date: November 29, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Kuan Su, Yu-Hong Pan, Jen-Pan Wang, Tong-Min Weng, Tsung-Han Wu