Abstract: An application-specific integrated circuit (ASIC) for use with a programmable I/O module includes programmable circuitry that enables the ASIC to be configured to support various different I/O functions. The ASIC includes a pin interface, a data interface, a digital section, and an analog section. The pin interface supports analog and digital signal communication and the data interface supports digital data communication. The digital section includes registers for storing digital data such as configuration commands, signal control commands, and digital signal information. The analog section is in electrical signal communication with pin interface and digital data communication with the registers.

Abstract: Disclosed are various embodiments of temperature-compensated relaxation oscillator circuits that may be fabricated using conventional CMOS manufacturing techniques. The relaxation oscillator circuits described herein exhibit superior low temperature coefficient performance characteristics, and do not require the use of expensive off-chip high precision resistors to effect temperature compensation. Positive and negative temperature coefficient resistors arranged in a resistor array offset one another to provide temperature compensation in the relaxation oscillator circuit.

Abstract: An error detector for a pseudo-random bit sequence (PRBS). A plurality of bits of a PRBS are received in a predictor circuit. A comparator compares two of the bits to predict a next bit in the sequence. The predicted next bit is compared with the actual next bit that is received to determine if there is an error in the actual next bit, and if so, the actual next bit is corrected accordingly. The erroneous actual next bit is replaced with the corrected actual next bit and is then used to predict a future actual next bit. A trigger circuit delays correction during initial operation until the predictor contains a bit sequence in which no errors have been detected.

Abstract: An application-specific integrated circuit (ASIC) for use with a programmable I/O module includes programmable circuitry that enables the ASIC to be configured to support various different I/O functions. The ASIC includes a pin interface, a data interface, a digital section, and an analog section. The pin interface supports analog and digital signal communication and the data interface supports digital data communication. The digital section includes registers for storing digital data such as configuration commands, signal control commands, and digital signal information. The analog section is in electrical signal communication with pin interface and digital data communication with the registers.

Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.

Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

Abstract: A stacked die integrated circuit assembly comprising: 1) a substrate; 2) a first integrated circuit die mounted on the substrate; 3) a copper interposer mounted on the first integrated circuit die; and 4) a second integrated circuit die mounted on the copper interposer. The copper interposer significantly reduces the warping of the stacked die IC assembly caused by the warping of the substrate due to thermal changes in the substrate. The copper interposer has a significantly higher coefficient of thermal expansion than a conventional silicon (Si) interposer. The higher CTE enables the copper interposer to counteract the substrate warping.

Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

Abstract: An error detector for a pseudo-random bit sequence (PRBS). A plurality of bits of a PRBS are received in a predictor circuit. A comparator compares two of the bits to predict a next bit in the sequence. The predicted next bit is compared with the actual next bit that is received to determine if there is an error in the actual next bit, and if so, the actual next bit is corrected accordingly. The erroneous actual next bit is replaced with the corrected actual next bit and is then used to predict a future actual next bit. A trigger circuit delays correction during initial operation until the predictor contains a bit sequence in which no errors have been detected.