Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Abstract: The present invention is to provide a high voltage over-current protection device and a manufacturing method thereof, in which PTC polymers are cross-linked by chemical cross-linking. With the method of the present invention, the high voltage endurance of the PTC devices is enhanced. In addition, the internal stress and degradation of polymers caused by irradiation treatment are prevented.

Abstract: The present invention discloses a conductive composition comprising a plurality of polymers and at least one conductive filler. The polymers are compatible under a molecular size and the form of the conductive filler includes a flake. The conductive composition of the present invention owns better electrical characteristics than a conventional conductive composition that comprises a single polymer. The present invention further discloses an over-current protection device comprising two metal foils and a PTC (positive temperature coefficient; PTC) composition layer. The PTC composition layer contains the conductive composition.

Abstract: A bias compensation self-aligned contact (SAC) etch endpoint detecting system is provided. The system includes an etch reactant chamber, an ESC power supply, and a signal processing computer. The etch reactant chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC supports a substrate having an interlevel dielectric (ILD) layer to be etched. The ESC power supply is coupled to the ESC and is configured to function as a bias compensating power supply. The signal processing computer monitors a bias compensation signal generated by the ESC power supply. The etch process to be carried out in the etch reactant chamber is configured to be discontinued when the bias compensation signal is determined to have a previously ascertained characteristic evidencing an etch endpoint of the ILD layer.

Abstract: A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

Abstract: A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

Abstract: A radio transmitter includes a high frequency circuit for modulation and transmitting during a remote transmitting mode and for receiving and demodulation during a receiving learning mode, a LED indicator connected in series between the high frequency circuit and the power supply for transmitting indication and tuning indication, a single chip microcomputer for identification code checking and code encoding control, and a memory (EEPROM) for data storage.

Abstract: A method for forming a patterned metal layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket metal layer. There is then formed over the blanket metal layer a patterned photoresist layer. There is then etched through use of a plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the blanket metal layer to form a patterned metal layer. The patterned metal layer so formed has a metal impregnated carbonaceous polymer residue layer formed upon a sidewall of the patterned metal layer. There is then stripped from the patterned metal layer the patterned photoresist layer through use of an oxygen containing plasma while simultaneously oxidizing the metal impregnated carbonaceous polymer residue layer to form an oxidized metal impregnated polymer residue layer upon the sidewall of the patterned metal layer.

Abstract: A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer.