Patents by Inventor Tong Yan Tee
Tong Yan Tee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8800391Abstract: A force sensor to measure a force from a load includes a plunger, a flexible disc-shaped membrane, a support plate and a silicon die. The plunger is configured to receive the force from the load, and has a ring-shaped groove at the lower surface. The membrane has a ring-shaped upper bump at the upper surface configured to complementarily fit into the groove at the lower surface of plunger and a ring-shaped lower bump at lower upper surface. The support plate has a ring-shaped groove for complementary fit into the lower bump on the lower surface of the membrane. The silicon die is centrally mounted on the membrane and comprises piezo-resistors with resistance that varies when deformed by the force. Force received by the plunger is transmitted to the membrane, causing the membrane to flex and bending or compressing of the silicon die, resulting in the measurement of the force.Type: GrantFiled: May 11, 2007Date of Patent: August 12, 2014Assignee: STMicroelectronics Asia Pacific Pte, Ltd.Inventors: Xueren Zhang, Andrea Lorenzo Vitali, Federico Giovanni Ziglioli, Bruno Biffi, Tong Yan Tee
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Patent number: 8642396Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.Type: GrantFiled: August 2, 2011Date of Patent: February 4, 2014Assignee: STMicroelectronics, Inc.Inventors: Kim-yong Goh, Tong-yan Tee
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Patent number: 8592980Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.Type: GrantFiled: March 7, 2007Date of Patent: November 26, 2013Assignee: STMicroelectronics Asia Pacific Pte., Ltd.Inventors: Shanzhong Wang, Valeriy Nosik, Tong Yan Tee, Xueren Zhang
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Patent number: 8524531Abstract: Solder joint reliability in an integrated circuit package is improved. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.Type: GrantFiled: November 8, 2012Date of Patent: September 3, 2013Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Tong Yan Tee
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Patent number: 8486824Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.Type: GrantFiled: July 10, 2012Date of Patent: July 16, 2013Assignees: STMicroelectronics Asia Pacific PTE., Ltd., Nanyang Technological UniversityInventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
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Publication number: 20130012016Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.Type: ApplicationFiled: July 10, 2012Publication date: January 10, 2013Applicant: STMicroelectronics Asia Pacific PTE LtdInventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
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Patent number: 8330258Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.Type: GrantFiled: December 24, 2003Date of Patent: December 11, 2012Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Tong Yan Tee
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Patent number: 8217518Abstract: A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material.Type: GrantFiled: March 7, 2007Date of Patent: July 10, 2012Assignees: STMicroelectronics Asia Pacific Pte., Ltd., Nanyang Technological UniversityInventors: Tong Yan Tee, Xueren Zhang, Shanzhong Wang, Valeriy Nosik, Jijie Zhou, Sridhar Idapalapati, Subodh Mhaisalkar, Zhi Yuan Shane Loo
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Publication number: 20120028397Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.Type: ApplicationFiled: August 2, 2011Publication date: February 2, 2012Applicant: STMicroelectronics Asia Pacific PTE Ltd.Inventors: Kim-yong Goh, Tong-yan Tee
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Patent number: 8018036Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.Type: GrantFiled: November 20, 2006Date of Patent: September 13, 2011Assignee: STMicroelectronics Asia Pacific Pte. Ltd.Inventors: Kim-yong Goh, Tong-yan Tee
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Publication number: 20080178691Abstract: A force sensor to measure a force from a load. The force sensor includes a plunger, a flexible disc-shaped membrane, a support plate and a silicon die. The plunger is configured to receive the force from the load, and has a ring-shaped groove at the lower surface. The membrane has a ring-shaped upper bump at the upper surface, wherein the upper bump is configured to complementarily fit into the groove at the lower surface of plunger. Furthermore, the membrane has a ring-shaped lower bump at lower upper surface. The support plate has a ring-shaped groove that is configured so that the lower bump on the lower surface of the membrane can complementarily fit into. The silicon die is centrally mounted on the membrane, where the silicon die comprises piezo-resistors that vary their resistance when deformed by the force.Type: ApplicationFiled: May 11, 2007Publication date: July 31, 2008Applicant: STMicroelectronics Asia Pacific PTE LtdInventors: Xueren Zhang, Andrea Lorenzo Vitali, Federico Giovanni Ziglioli, Bruno Biffi, Tong Yan Tee
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Publication number: 20070114641Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.Type: ApplicationFiled: November 20, 2006Publication date: May 24, 2007Applicant: STMicroelectronics Asia Pacific PTE LtdInventors: Kim-yong Goh, Tong-yan Tee
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Patent number: 7196425Abstract: A stacked die integrated circuit assembly comprising: 1) a substrate; 2) a first integrated circuit die mounted on the substrate; 3) a copper interposer mounted on the first integrated circuit die; and 4) a second integrated circuit die mounted on the copper interposer. The copper interposer significantly reduces the warping of the stacked die IC assembly caused by the warping of the substrate due to thermal changes in the substrate. The copper interposer has a significantly higher coefficient of thermal expansion than a conventional silicon (Si) interposer. The higher CTE enables the copper interposer to counteract the substrate warping.Type: GrantFiled: September 30, 2004Date of Patent: March 27, 2007Assignee: STMicroelectronics, Inc.Inventors: Anthony M. Chiu, Tong Yan Tee