Abstract: A video data processing method, system and apparatus, and a computer readable storage medium are disclosed. The video data processing method includes: when a reading signal is received, determining a storage space where video data to be compressed corresponding to the reading signal is located; in response to a determination that the storage space is a DDR storage space, reading video data of a plurality of Blocks from the DDR storage space, sending the video data to be compressed in the video data to a compression module for compression, and storing video data other than the video data to be compressed into a RAM storage space; and in response to a determination that the storage space is the RAM storage space, reading the video data to be compressed from the RAM storage space, and sending the video data to be compressed to the compression module for compression.

Abstract: Disclosed in the present disclosure are a video compression system and a server. The video compression system includes a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module; the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to write test data into the FIFO array module based on the first enable signal; and the read control module is configured to read the test data from the FIFO array module based on the first enable signal and transmit the test data to the hardware detection module.

Abstract: Disclosed in the present disclosure are a video compression system and a server. The video compression system includes a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module; the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to write test data into the FIFO array module based on the first enable signal; and the read control module is configured to read the test data from the FIFO array module based on the first enable signal and transmit the test data to the hardware detection module.

Abstract: The present application discloses method for transmitting video data, applied to chip for substrate management control. The method includes: respectively storing video compression data into first storage space and second storage space according to ping-pong operation structure; reading data of the same byte length from the first storage space and the second storage space; determining whether similarity between first data to be transmitted and second data to be transmitted is greater than or equal to preset value; if yes, setting the first data to be transmitted added with first transmission identifier as the current frame of data, and setting a second transmission identifier corresponding to the first transmission identifier as the next frame of data; and sending the current frame data and the next frame data to video data receiving end.

Abstract: The present application discloses a branch instruction processing method, system, and device, and a computer storage medium. The method includes: determining, on the basis of a target branch instruction, a branch instruction to be predicted (S101); predicting, on the basis of a plurality of preset branch prediction methods, the branch instruction to be predicted, so as to obtain a corresponding prediction result (S102); determining the prediction accuracy of each branch prediction method on the basis of the prediction result (S103); determining the branch prediction method corresponding to the highest prediction accuracy as a target branch prediction method (S104); and performing branch prediction on the target branch instruction on the basis of the target branch prediction method (S105).

Abstract: Disclosed are a method and apparatus for processing video compression. The method includes: controlling a comparison apparatus to perform frame-wise writing of original video data to an external storage apparatus, and controlling a video compression control component to perform frame-wise reading of the original video data from the external storage apparatus; in response to writing original video data of a non-first frame into the external storage apparatus, and if yes, and in response to writing the original video data of the current frame into the external storage apparatus, converting the video data into tag information and writing the tag information into the external storage apparatus; and in response to reading the original video data of the previous frame from the external storage apparatus, writing the video data corresponding to the current same line number into an internal storage apparatus.

Abstract: A monitoring video compression method, a monitoring system, a computer device, and a medium. The method includes: a monitoring center configuring a key monitoring point and sending configuration information of the key monitoring point to a video server through a management center; the video server receiving the configuration information of the key monitoring point, selecting a corresponding video source based on the configuration information of the key monitoring point, transferring the corresponding video source from a video compression module to a baseboard management controller (BMC) for compression, and writing the corresponding video source into a storage space of the video server after the compression is completed.

Abstract: Disclosed in the present application is a video data transmission method, which is applied to a substrate management control chip. The video data transmission method comprises: respectively storing compressed video data in a first storage space and a second storage space according to a ping-pong operation structure; reading data of the same byte length from the first storage space and the second storage space; determining whether the similarity between first data to be transmitted and second data to be transmitted is greater than or equal to a preset value; if so, setting, as the current frame of data, said first data to which a first transmission identifier is added, and setting, as the next frame of data, a second transmission identifier corresponding to the first transmission identifier; and sending the current frame of data and the next frame of data to a video data receiving end.

Abstract: A method, system and device for pipeline processing of instructions and a computer storage medium. The method comprises: acquiring a target instruction set (S101); acquiring a target prediction result, wherein the target prediction result is a result obtained by predicting a jump mode of the target instruction set (S102); performing pipeline processing on the target instruction set according to the target prediction result (S103); determining if a pipeline flushing request is received (S104); and if so, correspondingly saving the target instruction set and a corresponding pipeline processing result, so as to perform pipeline processing on the target instruction set again on the basis of the pipeline processing result (S105).

Abstract: A video storage method and apparatus, and a system on chip (SOC) system and a medium. The method includes: according to video information to be stored and occupation information of a target double data rate (DDR), sending a storage space application request to the target DDR (S11); receiving a storage space allocation response sent by the target DDR according to the storage space application request (S12); and storing video data to be stored, which corresponds to the video information to be stored, in an address space which is in the target DDR and corresponds to the storage space application request (S13). By means of the present application, the wasting of a storage space can be avoided, and when video storage is not needed, a storage resource on a SOC system can be used for supporting the operation of other functions.

Abstract: A data transmission method applied to an APB bridge for connecting an APB and an AHB, includes: dividing transmission into an address phase and a data phase according to a feature of an AHB; in the address phase, when the AHB meets an address transmission condition corresponding to a current operation, transmitting address information and control information, which are sent by the AHB, to an APB; and in the data phase, when the APB meets a valid data transmission condition corresponding to the current operation, sending received data to a bus corresponding to the current operation, wherein the bus is the APB or the AHB. According to the present application, the address information, the control information, and the data do not need to be cached, whereby the occupation of a storage space is reduced. Further disclosed are a data transmission apparatus and an electronic device having the above beneficial effects.

Abstract: A method, system and device for pipeline processing of instructions and a computer storage medium. The method comprises: acquiring a target instruction set (S101); acquiring a target prediction result, wherein the target prediction result is a result obtained by predicting a jump mode of the target instruction set (S102); performing pipeline processing on the target instruction set according to the target prediction result (S103); determining if a pipeline flushing request is received (S104); and if so, correspondingly saving the target instruction set and a corresponding pipeline processing result, so as to perform pipeline processing on the target instruction set again on the basis of the pipeline processing result (S105).

Abstract: Disclosed is a baseboard management controller constructed based on RISC-V system architecture, wherein the baseboard management controller includes a processor, a memory and a peripheral interface that are connected by an AXI bus; wherein, the memory is configured to store an OpenBMC system which is obtained by cross-compiling of an OpenBMC software framework by an RISC-V tool chain of the RISC-V architecture; the processor is configured to execute the OpenBMC system stored in the memory, and the soft core source code of the processor is generated by a RocketChip generator. The baseboard management controller is constructed based on the open source RISC-V system architecture instead of the ARM architecture. As a result, the baseboard management controller used by the user is no longer limited by the manufacturer, and the user can completely autonomously control the baseboard management controller that he/she uses.

Abstract: A RISC-V branch prediction method and device, an electronic device and a computer readable storage medium are provided. On the basis of the prior art, the remaining jump times of the jump instruction are additionally acquired, and the single jump step length (the single jump step length is not fixed to be 1) is calculated according to the difference of remaining jump times during two consecutive jumps, whether the target jump instruction has executed the last jump can be judged according to the single jump step length of a jump instruction and in combination with the real-time remaining jump times, so as to determine the jump times that need to be executed subsequently according to the judgment result.