Patents by Inventor Tong Qing Chen
Tong Qing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150050811Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.Type: ApplicationFiled: October 29, 2014Publication date: February 19, 2015Inventors: Sohan Mehta, Tong Qing Chen, Vikrant Chauhan, Ravi Srivastava, Catherine Labelle, Mark Kelling
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Patent number: 8932961Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.Type: GrantFiled: February 13, 2012Date of Patent: January 13, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Sohan Mehta, Tong Qing Chen, Vikrant Chauhan, Ravi Srivastava, Catherine Labelle, Mark Kelling
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Publication number: 20130207108Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Sohan Mehta, Tong Qing Chen, Vikrant Chauhan, Ravi Srivastava, Catherine Labelle, Mark Kelling
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Patent number: 8304834Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: GrantFiled: August 22, 2006Date of Patent: November 6, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Patent number: 8102054Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 23, 2010Date of Patent: January 24, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Publication number: 20100314774Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: ApplicationFiled: August 23, 2010Publication date: December 16, 2010Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
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Patent number: 7803704Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: GrantFiled: August 22, 2008Date of Patent: September 28, 2010Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Bei Chao Zhang, Chim Seng Seet, Juan Boon Tan, Fan Zhang, Yong Chiang Ee, Bo Tao, Tong Qing Chen, Liang Choo Hsia
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Publication number: 20100044869Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.Type: ApplicationFiled: August 22, 2008Publication date: February 25, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Bei Chao ZHANG, Chim Seng SEET, Juan Boon TAN, Fan ZHANG, Yong Chiang EE, Bo TAO, Tong Qing CHEN, Liang Choo HSIA
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Patent number: 7553758Abstract: Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.Type: GrantFiled: September 18, 2006Date of Patent: June 30, 2009Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd., International Business Machines CorporationInventors: Wan-jae Park, Hyung-yoon Choi, Yi-hsiung Lin, Tong Qing Chen
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Patent number: 7524755Abstract: A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.Type: GrantFiled: February 22, 2006Date of Patent: April 28, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Johnny Widodo, Bei Chao Zhang, Tong Qing Chen, Yong Kong Siew, Fan Zhang, San Leong Liew, John Sudijono, Liang Choo Hsia
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Patent number: 7488687Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.Type: GrantFiled: September 12, 2006Date of Patent: February 10, 2009Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd., International Business Machines CorporationInventors: Wan Jae Park, Jae Hak Kim, Tong Qing Chen, Yi-hsiung Lin
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Publication number: 20080070409Abstract: Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.Type: ApplicationFiled: September 18, 2006Publication date: March 20, 2008Inventors: Wan-jae Park, Hyung-yoon Choi, Yi-hsiung Lin, Tong Qing Chen
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Publication number: 20080064199Abstract: Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer.Type: ApplicationFiled: September 12, 2006Publication date: March 13, 2008Inventors: Wan Jae Park, Jae Hak Kim, Tong Qing Chen, Yi-hsiung Lin
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Publication number: 20060281253Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: ApplicationFiled: August 22, 2006Publication date: December 14, 2006Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Patent number: 7119005Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: GrantFiled: January 27, 2005Date of Patent: October 10, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Patent number: 6884712Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: GrantFiled: February 7, 2003Date of Patent: April 26, 2005Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Zhen Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
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Publication number: 20040155269Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: ApplicationFiled: February 7, 2003Publication date: August 12, 2004Applicant: Chartered Semiconductor Mfg. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah