Patents by Inventor Tongyu Song
Tongyu Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230422140Abstract: The present invention provides a method for optimizing the energy efficiency of wireless sensor network based on the assistance of unmanned aerial vehicle, firstly, collecting the state of the WSN through current routing scheme, and inputting the state of the WSN into the decision network of the agent to determine a next hover node; Secondly, based on the location of the next hover node, generating a new routing scheme by the UAV, and sending each sensor node's routing to its corresponding sensor node through current routing by the UAV; Lastly, after all sensor nodes have received their routings respectively, all sensor nodes send their collected data to the hover node through their routings respectively, and the UAV flies to and hovers above the next hover node to collect data through the next hover node, thus the data collection of the whole WSN is completed.Type: ApplicationFiled: September 12, 2023Publication date: December 28, 2023Applicant: University of Electronic Science and Technology of ChinaInventors: Jing REN, Jianxin LIAO, Tongyu SONG, Chao SUN, Jiangong ZHENG, Xiaotong GUO, Sheng WANG, Shizhong XU, Xiong WANG
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Publication number: 20230231796Abstract: A method for energy efficient routing in wireless sensor network based on multi-agent deep reinforcement learning, predefines a to-be-deployed wireless sensor network and creates a cooperative routing decision system including A decision networks and one sink module, A decision networks deployed on the agents ai, i=1, 2, . . . , A, of the sensor nodes, the sink module deployed on the sink node n0. The decision network obtains a probability vector according to its local observation and position vectors. The sink module calculates a routing for each sensor node according the probability vectors of A decision networks and sends the routings to corresponding sensor nodes. A multi-agent deep reinforcement learning algorithm is adopted to train the decision networks of A agents ai, i=1, 2, . . . , A of the cooperative routing decision system, deploys the to-be-deployed wireless sensor network into an environment and updates the routing policy of the deployed wireless sensor network at each update cycle of routing.Type: ApplicationFiled: March 24, 2023Publication date: July 20, 2023Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINAInventors: Jing REN, Tongyu SONG, Jiangong ZHENG, Xiaotong GUO, Xuebin TAN, Sheng WANG, Shizhong XU, Xiong WANG
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Patent number: 10985737Abstract: A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.Type: GrantFiled: July 18, 2019Date of Patent: April 20, 2021Assignee: QUALCOMM IncorporatedInventor: Tongyu Song
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Patent number: 10663993Abstract: A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage regulator also includes a feedforward path to extend the band reject PSRR.Type: GrantFiled: September 19, 2016Date of Patent: May 26, 2020Assignee: QUALCOMM INCORPORATEDInventors: Tongyu Song, Jeffrey Mark Hinrichs
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Publication number: 20200028495Abstract: A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.Type: ApplicationFiled: July 18, 2019Publication date: January 23, 2020Inventor: Tongyu SONG
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Publication number: 20180017982Abstract: A voltage regulator includes a band limited reference voltage. The band limited reference voltage is generated from a supply voltage combined with a feedback path to provide a band reject power supply rejection ratio (PSRR). The voltage regulator also includes a feedforward path to extend the band reject PSRR.Type: ApplicationFiled: September 19, 2016Publication date: January 18, 2018Inventors: Tongyu SONG, Jeffrey Mark HINRICHS
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Patent number: 9379727Abstract: A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.Type: GrantFiled: February 23, 2015Date of Patent: June 28, 2016Assignee: QUALCOMM IncorporatedInventors: Dongwon Seo, Yang You, Honghao Ji, Tongyu Song, Ganesh Saripalli, Shahin Mehdizad Taleie
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Publication number: 20150318863Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.Type: ApplicationFiled: January 29, 2015Publication date: November 5, 2015Inventors: Tongyu SONG, Derui KONG
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Publication number: 20150311910Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a current comparator circuit associated with a DAC element. The apparatus receives an output of a current comparator module, determines calibration data using a finite state machine (FSM) based on the output of the current comparator module, and reduces an offset current at an input of the current comparator module based on the calibration data from the FSM.Type: ApplicationFiled: January 20, 2015Publication date: October 29, 2015Inventors: Tongyu SONG, Derui KONG
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Patent number: 9160357Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.Type: GrantFiled: January 29, 2015Date of Patent: October 13, 2015Assignee: QUALCOMM IncorporatedInventors: Tongyu Song, Derui Kong
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Patent number: 8872685Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: QUALCOMM IncorporatedInventors: Tongyu Song, Sang Min Lee, Derui Kong, Dongwon Seo
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Patent number: 8847801Abstract: Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.Type: GrantFiled: February 27, 2013Date of Patent: September 30, 2014Assignee: QUALCOMM IncorporatedInventor: Tongyu Song
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Publication number: 20140266830Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Tongyu Song, Sang Min Lee, Derui Kong, Dongwon Seo
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Publication number: 20140240152Abstract: Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: QUALCOMM INCORPORATEDInventor: Tongyu Song
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Patent number: 8564346Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).Type: GrantFiled: January 23, 2012Date of Patent: October 22, 2013Assignee: QUALCOMM IncorporatedInventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi
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Publication number: 20120161837Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).Type: ApplicationFiled: January 23, 2012Publication date: June 28, 2012Inventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi
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Patent number: 8169353Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.Type: GrantFiled: January 13, 2010Date of Patent: May 1, 2012Assignee: QUALCOMM, IncorporatedInventors: Dongwon Seo, Ganesh R Saripalli, Tongyu Song, Shahin Mehdizad Taleie, Derui Kong
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Patent number: 8169243Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.Type: GrantFiled: April 2, 2009Date of Patent: May 1, 2012Assignee: Qualcomm IncorporatedInventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi
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Publication number: 20110074615Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.Type: ApplicationFiled: January 13, 2010Publication date: March 31, 2011Applicant: QUALCOMM INCORPORATEDInventors: Dongwon Seo, Ganesh R. Saripalli, Tongyu Song, Shahin Mehdizad Taleie, Derui Kong
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Publication number: 20100253405Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.Type: ApplicationFiled: April 2, 2009Publication date: October 7, 2010Applicant: QUALCOMM IncorporatedInventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi