Patents by Inventor Toni Viki BRKIC
Toni Viki BRKIC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972503Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that includes an early culling tester that can access plural different culling test data buffers is disclosed. Information is maintained indicating which of the plural culling test data buffers is expected to be accessed, and the information is used to control the early culling tester. The information may be used to control the early culling tester such that processing delays associated with waiting for dependencies to resolve are reduced.Type: GrantFiled: May 6, 2022Date of Patent: April 30, 2024Assignee: Arm LimitedInventors: Toni Viki Brkic, Sandeep Kakarlapudi, Tord Kvestad Øygard, Saurav Arjun
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Publication number: 20240037692Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry including, inter alia, at least an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents, and an indication of whether the group of fragments that the list entry represents is eligible to undergo particular processing operations. The coverage information and eligibility information for the list entries is then used to control the processing of fragments for sub-regions of a tile, in such a way as to ensure that processing order dependencies are enforced and met.Type: ApplicationFiled: July 24, 2023Publication date: February 1, 2024Applicant: Arm LimitedInventors: William Robert Stoye, Olof Henrik Uhrenholt, Wing-Tsi Henry Wong, Edward Hardy, Toni Viki Brkic, Ole Magnus Ruud
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Publication number: 20240037853Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.Type: ApplicationFiled: July 24, 2023Publication date: February 1, 2024Applicant: Arm LimitedInventors: William Robert Stoye, Olof Henrik Uhrenholt, Wing-Tsi Henry Wong, Edward Hardy, Toni Viki Brkic, Ole Magnus Ruud
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Patent number: 11861760Abstract: A method of operating a tile-based graphics processor that executes a graphics processing pipeline is disclosed. When there are no more primitives left to be provided for processing to the pipeline for a rendering tile, it is determined whether any remaining processing steps for the rendering tile can be omitted, e.g. because they will not affect a buffer that will be output when the rendering tile is complete. When it is determined that a processing step can be omitted, that processing step is omitted.Type: GrantFiled: January 24, 2022Date of Patent: January 2, 2024Assignee: Arm LimitedInventor: Toni Viki Brkic
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Patent number: 11798121Abstract: A method of operating a tile-based graphics processing pipeline, in which the pipeline maintains information indicating whether sample values of rendered fragment data stored in the tile buffer for a set of plural pixels (or for each set of a plurality of sets of plural pixels) have the same value.Type: GrantFiled: January 25, 2022Date of Patent: October 24, 2023Assignee: Arm LimitedInventors: Jian Wang, Toni Viki Brkic
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Publication number: 20220366524Abstract: A graphics processor comprising a rasteriser, a renderer, and a fragment dependency manager, and a method of operating a graphics processor. The fragment dependency manager is operable to maintain plural queues, where each queue corresponds to a respective set of plural sets of one or more sampling points that an array of sampling points is divided into, and wherein each queue entry is indicative of one or more fragments that when processed by the renderer will produce rendered fragment data for one or more of the sampling points of the set of one or more sampling points to which the queue corresponds.Type: ApplicationFiled: May 9, 2022Publication date: November 17, 2022Inventors: Olof Henrik UHRENHOLT, Toni Viki BRKIC, Edward HARDY
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Publication number: 20220358616Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that includes an early culling tester that can access plural different culling test data buffers is disclosed. Information is maintained indicating which of the plural culling test data buffers is expected to be accessed, and the information is used to control the early culling tester. The information may be used to control the early culling tester such that processing delays associated with waiting for dependencies to resolve are reduced.Type: ApplicationFiled: May 6, 2022Publication date: November 10, 2022Inventors: Toni Viki BRKIC, Sandeep KAKARLAPUDI, Tord Kvestad ØYGARD, Saurav ARJUN
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Publication number: 20220277411Abstract: A method of operating a tile-based graphics processing pipeline, in which the pipeline maintains information indicating whether sample values of rendered fragment data stored in the tile buffer for a set of plural pixels (or for each set of a plurality of sets of plural pixels) have the same value.Type: ApplicationFiled: January 25, 2022Publication date: September 1, 2022Inventors: Jian WANG, Toni Viki BRKIC
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Publication number: 20220237730Abstract: A method of operating a tile-based graphics processor that executes a graphics processing pipeline is disclosed. When there are no more primitives left to be provided for processing to the pipeline for a rendering tile, it is determined whether any remaining processing steps for the rendering tile can be omitted, e.g. because they will not affect a buffer that will be output when the rendering tile is complete. When it is determined that a processing step can be omitted, that processing step is omitted.Type: ApplicationFiled: January 24, 2022Publication date: July 28, 2022Inventor: Toni Viki BRKIC
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Patent number: 11250611Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that can generate a render output using different shading rates is disclosed. First and second input shading rates are combined prior to rasterisation, and a combined shading rate may be propagated through the pipeline instead of the first and second input shading rates. The combined shading rate may then be combined with a third input shading rate at or after the rasterisation stage. This can reduce bandwidth, hardware and energy requirements.Type: GrantFiled: January 29, 2021Date of Patent: February 15, 2022Assignee: Arm LimitedInventors: Ole Magnus Ruud, Rafal Stepuch, Toni Viki Brkic
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Patent number: 11055904Abstract: A graphics processor includes a rasteriser, an early depth tester, a renderer, a late depth tester, and a depth test data buffer that stores depth data values for use by the early and late depth testers. When a fragment is to undergo an early depth test to update the depth buffer, it is first determined whether the fragment should undergo the early depth test to update the depth buffer without waiting for any other fragment to undergo a depth test, or whether the result of a late depth test on a fragment that is still to undergo a late depth test should be awaited before performing a depth test to update the depth buffer on the fragment.Type: GrantFiled: August 27, 2019Date of Patent: July 6, 2021Assignee: Arm LimitedInventors: Toni Viki Brkic, Reimar Gisbert Doffinger, Jakob Axel Fries, Sven Uwe Deidersen
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Publication number: 20210065437Abstract: A graphics processor includes a rasteriser, an early depth tester, a renderer, a late depth tester, and a depth test data buffer that stores depth data values for use by the early and late depth testers. When a fragment is to undergo an early depth test to update the depth buffer, it is first determined whether the fragment should undergo the early depth test to update the depth buffer without waiting for any other fragment to undergo a depth test, or whether the result of a late depth test on a fragment that is still to undergo a late depth test should be awaited before performing a depth test to update the depth buffer on the fragment.Type: ApplicationFiled: August 27, 2019Publication date: March 4, 2021Applicant: Arm LimitedInventors: Toni Viki Brkic, Reimar Gisbert Doffinger, Jakob Axel Fries, Sven Uwe Deidersen
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Method of and apparatus for generating a signature representative of the content of an array of data
Patent number: 10832639Abstract: A method and an apparatus for generating a signature representative of the content of a region of an array of data in a data processing system, where the region of the array of data comprising plural data positions, and each data position having an associated data value or values. A data value or values for a data position of the region of the data array is/are generated. The data value or values for the data position of the region of the data array is/are written to storage that stores the region of the data array as it is being generated. A signature representative of the content of the region of the data array is generated in parallel with the data value or values for the data position of the region of the data array being written to the storage.Type: GrantFiled: July 20, 2016Date of Patent: November 10, 2020Assignee: ARM LimitedInventors: Toni Viki Brkic, Jakob Axel Fries, Reimar Gisbert Döffinger -
Patent number: 10789768Abstract: A graphics processing apparatus comprises fragment generating circuitry to generate graphics fragments corresponding to graphics primitives, thread processing circuitry to perform threads of processing corresponding to the fragments, and forward kill circuitry to trigger a forward kill operation to prevent further processing of a target thread of processing corresponding to an earlier graphics fragment when the forward kill operation is enabled for the target thread and the earlier graphics fragment is determined to be obscured by one or more later graphics fragments. The thread processing circuitry supports enabling of the forward kill operation for a thread including at least one forward kill blocking instruction having a property indicative that the forward kill operation should be disabled for the given thread, when the thread processing circuitry has not yet reached a portion of the thread including the at least one forward kill blocking instruction.Type: GrantFiled: September 12, 2018Date of Patent: September 29, 2020Assignee: ARM LimitedInventors: Stephane Forey, Jørn Nystad, Reimar Gisbert Döffinger, Kenneth Edvard Østby, Toni Viki Brkic
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Patent number: 10769838Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.Type: GrantFiled: December 13, 2018Date of Patent: September 8, 2020Assignee: Arm LimitedInventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
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Patent number: 10726610Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.Type: GrantFiled: August 29, 2018Date of Patent: July 28, 2020Assignee: Arm LimitedInventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
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Publication number: 20200074721Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Applicant: Arm LimitedInventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
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Patent number: 10580113Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.Type: GrantFiled: October 5, 2018Date of Patent: March 3, 2020Assignee: Arm LimitedInventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
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Patent number: 10395394Abstract: A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides encoded blocks of fixed data size. The selection of which version of the encoded block to write out is based on the size of the encoded block when encoded using the first encoding scheme. This provides the potential for the encoded block that is written out to be compressed in a more superior manner using the first encoding scheme where possible, while also providing an encoded block that has a predictable maximum compressed size.Type: GrantFiled: May 31, 2017Date of Patent: August 27, 2019Assignee: Arm LimitedInventors: Lars Oskar Flordal, Jakob Axel Fries, Toni Viki Brkic
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Publication number: 20190188896Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.Type: ApplicationFiled: December 13, 2018Publication date: June 20, 2019Applicant: Arm LimitedInventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal