Abstract: A system includes a decision feedback equalizer (DFE). The DFE includes a first summing node, a first synchronization latch, a second synchronization latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronization latch receives data from the first summing node. The second synchronization latch and the first feedback latch receive data from the first synchronization latch. The first feedback shift register is coupled to an output of the second synchronization latch or the first feedback latch. The first feedback shift register includes sequentially coupled shift latches. A first of the shift latches data received from the second synchronization latch or the first feedback latch and provides data to the first summing node. First alternate ones of the shift latches are configured to provide feedback data to the first summing node.

Abstract: A driver circuit includes an input drive stage, an output drive stage, and a transformer. The input drive stage is configured to receive a differential input signal, and amplify the differential input signal. The output drive stage is coupled to the input drive stage, and is configured to receive amplified differential input signal from the input drive stage, and to further amplify the amplified differential input signal. The transformer is configured to transfer current from the output drive stage to the input drive stage.

Abstract: A driver circuit includes an input drive stage, an output drive stage, and a transformer. The input drive stage is configured to receive a differential input signal, and amplify the differential input signal. The output drive stage is coupled to the input drive stage, and is configured to receive amplified differential input signal from the input drive stage, and to further amplify the amplified differential input signal. The transformer is configured to transfer current from the output drive stage to the input drive stage.

Abstract: A system includes a decision feedback equalizer (DFE). The DFE includes a first summing node, a first synchronization latch, a second synchronization latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronization latch receives data from the first summing node. The second synchronization latch and the first feedback latch receive data from the first synchronization latch. The first feedback shift register is coupled to an output of the second synchronization latch or the first feedback latch. The first feedback shift register includes sequentially coupled shift latches. A first of the shift latches data received from the second synchronization latch or the first feedback latch and provides data to the first summing node. First alternate ones of the shift latches are configured to provide feedback data to the first summing node.

Abstract: Differential voltage mode signal driver circuitry is presented in which a differential current mode amplifier input stage provides a differential signal, and an output stage includes a pair of bipolar transistors receiving the differential signal and being connected in series with a pair of cross-coupled field effect transistors that are coupled to corresponding current sources, where a negative impedance circuit is connected between the field effect transistors to substantially cancel a parasitic capacitance of a driven output circuit.

Abstract: Differential voltage mode signal driver circuitry is presented in which a differential current mode amplifier input stage provides a differential signal, and an output stage includes a pair of bipolar transistors receiving the differential signal and being connected in series with a pair of cross-coupled field effect transistors that are coupled to corresponding current sources, where a negative impedance circuit is connected between the field effect transistors to substantially cancel a parasitic capacitance of a driven output circuit.

Abstract: A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream.

Abstract: A low-voltage high-speed frequency divider substantially reduces the power required to generate a half-rate in-phase clock signal and a half-rate quadrature-phase clock signal by reducing the number of pairs of transistors that respond to a full-rate clock signal and a full-rate inverse clock signal.

Abstract: A low-voltage high-speed frequency divider substantially reduces the power required to generate a half-rate in-phase clock signal and a half-rate quadrature-phase clock signal by reducing the number of pairs of transistors that respond to a full-rate clock signal and a full-rate inverse clock signal.

Abstract: A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream.